MULTIPLE ENDIANNESS COMPATIBILITY

• US 20160110135A1
• Filed: 10/16/2015
• Published: 04/21/2016
• Est. Priority Date: 10/16/2014
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Wheeler, Kyle B., Finkbeiner, Timothy P., Willcock, Jeremiah J.
• Granted Patent: US 10,163,467 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating

Abstract

Examples of the present disclosure provide apparatuses and methods for multiple endianness compatibility. An example method comprises receiving a plurality of bytes in a non-bit-sequential format. The method includes reordering the bits in each byte of the plurality of bytes such that the plurality of bytes are arranged in a bit-sequential format.

Claims

1. A method, comprising:

receiving a plurality of bytes in a non-bit-sequential format; and

reordering, using reordering circuitry, the bits in each byte of the plurality of bytes such that the plurality of bytes are arranged in a bit-sequential format.

2. The method of claim 1, wherein the bit-sequential format is a bit-sequential little endian format where the bits are arranged from a least significant bit of each byte of the plurality of bytes being stored in a most significant position and a most significant bit of each byte of the plurality of bytes being stored in a least significant position.

3. The method of claim 1, wherein the plurality of bytes are received at a memory device.

4. The method of claim 1, further comprising storing the plurality of bytes arranged in the bit-sequential format in an array of memory cells, wherein the plurality of bytes are stored in cells coupled to a same access line of the array.

5. The method of claim 1, wherein the reordering is performed independent of the number of bytes.

6. The method of claim 1, comprising performing a number of shift operations on the bits arranged in the bit-sequential format.

7. The method of claim 6, wherein:

each of the number of bits is stored in one of a respective number of compute components; and

performing the number of shift operations comprises shifting each of the number of bits from a compute component coupled to a memory cell storing a lesser significant bit to a compute component coupled to a memory cell storing a more significant bit.

8. The method of claim 6, wherein:

each of the number of bits is stored in one of a respective number of compute components; and

performing the number of shift operations comprises shifting each of the number of bits from a compute component coupled to a memory cell storing a more significant bit to a compute component coupled to a memory cell storing a lesser significant bit.

9. The method of claim 6, comprising reordering the bits from a bit-sequential little endian format to a non-bit-sequential little endian format on a byte-by-byte basis after the number of shift operations are performed.

10. The method of claim 8, comprising sending the reordered bits to a processing resource.

11. The method of claim 1, wherein reordering the bits in each byte comprises reordering a most significant bit of a first byte from a most significant bit position to a least significant bit position.

12. The method of claim 11, wherein reordering the bits in each byte comprises reordering a least significant bit of the first byte from a least significant bit position to the most significant bit position.

13. The method of claim 12, wherein reordering the bits in each byte comprises reordering:

a second most significant bit of the first byte from a second most significant bit position to a seventh most significant bit position;

a third most significant bit of the first byte from a third most significant bit position to a sixth most significant bit position;

a fourth most significant bit of the first byte from a fourth most significant bit position to a fifth most significant bit position

a fifth most significant bit of the first byte from a fifth most significant bit position to a fourth most significant bit position;

a sixth most significant bit of the first byte from a sixth most significant bit position to a third most significant bit position; and

a seventh most significant bit of the first byte from a seventh most significant bit position to a second most significant bit position.

14. A method, comprising:

on a bytewise basis, reversing, via reordering circuitry, an order of bits of a plurality of bytes stored in a group of memory cells in a bit-sequential little endian format; and

providing the reversed bits in a bytewise little endian format.

15. The method of claim 14, wherein a first bit position in the order is a most significant bit position and an eighth bit position in the order is a least significant bit position.

16. The method of claim 15, wherein the bits are ordered in a bit-sequential little endian format, prior to the reversing, such that a most significant bit of a first byte is in a least significant bit position of the first byte.

17. The method of claim 16, wherein the bits are ordered in a bit-sequential little endian format, prior to the reversing, such that a least significant bit of the first byte is in a most significant bit position of the first byte.

18. The method of claim 17, wherein the bits are ordered in a bit-sequential little endian format, prior to the reversing, such that:

a second most significant bit is in a seventh most significant bit position of the first byte;

a third most significant bit is in a sixth most significant bit position of the first byte; and

a fourth most significant bit is in a fifth most significant bit position of the first byte;

a fifth most significant bit is in a fourth most significant bit position of the first byte;

a sixth most significant bit is in a third most significant bit position of the first byte; and

a seventh most significant bit is in a second most significant bit position of the first byte.

19. The method of claim 14, wherein providing the reversed bits in a bytewise little endian format comprises providing the reversed bits to a host.

20. The method of claim 19, wherein the reversed bits are ordered in a bytewise little endian format such that:

a most significant bit of the first byte is in a most significant bit position of the first byte; and

a least significant bit of the first byte is in a least significant bit position of the first byte.

21. An apparatus comprising:

a memory array;

a controller coupled to the memory array; and

I/O circuitry coupled to the memory array and the controller, wherein the I/O circuitry includes reordering circuitry configured to

reorder bits of a plurality of bytes received in a bytewise little endian bitwise big endian format from the bitwise big endian format to a bitwise little endian format by reversing the bits on a bytewise basis.

22. The apparatus of claim 21, wherein the controller is configured to cause the reversed bits in the bitwise little endian format to be stored in a group of memory cells of the memory array.

23. The apparatus of claim 21, wherein the reordering circuitry is configured to reorder the bits without knowing a data format or how many of the bytes are stored in the group of memory cells.

24. The apparatus of claim 21, wherein the apparatus is further configured to perform a number of operations including shift operations.

25. The apparatus of claim 24, wherein the apparatus is configured to perform the number of shift operations in a first direction on bits ordered in a bitwise big endian format.

26. The apparatus of claim 25, wherein the number of shifts in the first direction is a number of shifts toward a less significant bit position.

27. The apparatus of claim 25, wherein the apparatus is configured to perform the number of shift operations in a different direction than the first direction when the received bits of the plurality of bytes are received in a bitwise little endian, bytewise big endian format to reorder a least significant byte from a least significant byte position to a most significant byte position.

28. The apparatus of claim 27, wherein the apparatus configured to perform the number of shift operations in the different direction includes shifting a second least significant byte from a second least significant byte position to a second most significant byte position.

29. An apparatus comprising:

a memory array; and

reordering circuitry coupled to the memory array and configured to reorder bits of a plurality of bytes received in a bytewise little endian bitwise big endian format to a bitwise little endian format; and

a controller configured to;

cause the reordered bits to be stored in a group of memory cells; and

cause a number of shift operations to be performed on the reordered bits.

30. The apparatus of claim 29, wherein the reordering circuitry resides in the controller.

31. The apparatus of claim 29, wherein the memory array includes a number of compute components coupled to a number of corresponding sense lines of the memory array.