DATA CACHE AND METHOD FOR DATA CACHING

• US 20160110290A1
• Filed: 10/14/2015
• Published: 04/21/2016
• Est. Priority Date: 10/20/2014
• Status: Abandoned Application

• Current Assignee: Emc IP Holding Company LLC (Dell Technologies Inc.)
• Original Assignee: EMC Corporation (Dell Technologies Inc.)
• Inventors: Chen, Ted Huaqi, Zheng, Tao
• Application Number:
  US14/883,138
• Publication Number:
  US 20160110290A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/222 Non-volatile memory
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices

Abstract

Embodiments of the present invention disclose a data cache and a system, a computer program product and a method for data caching, wherein a data cache includes: at least one memory bank adapted for enabling high-speed data access; and at least one converter configured to receive a first instruction for a data access operation, and convert the first instruction to a second instruction compatible with the at least one memory bank so as to perform the data access operation, the first instruction being transmitted from a high-speed bus interface of a host device to the data cache.

Claims

1. A data cache, comprising:

at least one memory bank adapted for enabling high-speed data access; and

at least one converter configured to receive a first instruction for a data access operation, and convert the first instruction to a second instruction compatible with the at least one memory bank so as to perform the data access operation, the first instruction being transmitted from a high-speed bus interface of a host device to the data cache.

2. The data cache according to claim 1, wherein the at least one converter comprises a plurality of converters, and the data cache further comprising:

a high-speed bus interface switch configured to couple the plurality of converters to the high-speed bus interface of the host device and to assign the first instruction to the plurality of converters.

3. The data cache according to claim 1, wherein the at least one memory bank comprises a plurality of memory banks, and the data cache further comprising:

a buffer configured to couple the plurality of memory banks to the at least one converter and to assign the second instruction to the plurality of memory banks.

4. The data cache according to claim 3, wherein the first instruction is transmitted to the data cache from the high-speed bus interface of the host device through a host bus adapter.

5. The data cache according to claim 3, wherein the high-speed bus interface comprises a peripheral component interconnection express (PCIe) bus interface.

6. The data cache according to claim 3, wherein the memory bank comprises at least one double data rate (DDR) memory.

7. The data cache according to claim 6, wherein the DDR memory comprises a non-volatile dual in-line memory module (NVDIMM).

8. A method for data caching, comprising:

receiving a first instruction for a data access operation, the first instruction being transmitted from a high-speed bus interface of a host device to a data cache; and

converting the first instruction into a second instruction compatible with at least one memory bank so as to perform the data access operation, the at least one memory bank being adapted for enabling high-speed data access.

9. The method according to claim 8, wherein receiving the first instruction for the data access operation comprises:

receiving the first instruction from the high-speed bus interface of the host device via a high-speed bus interface switch; and

assigning the first instruction to a plurality of converters from the high-speed bus interface switch for the converting.

10. The method according to claim 8, wherein the at least one memory bank comprises a plurality of memory banks, the method further comprising:

transmitting the second instruction to a buffer coupled to the plurality of memory banks; and

assigning the second instruction from the buffer to the plurality of memory banks.

11. The method according to claim 10, wherein the first instruction is transmitted to the data cache from the high-speed bus interface of the host device through a host bus adapter.

12. The method according to claim 10, wherein the high-speed bus interface comprises a peripheral component interface express (PCIe) bus interface.

13. The method according to claim 10, wherein the memory bank comprises at least one double data rate (DDR) memory.

14. The method according to claim 13, wherein the DDR memory comprises a non-volatile dual in-line memory module (NVDIMM).

15. A computer program product for data caching, computer program product comprising:

a non-transient computer readable medium encoded with computer executable program code, the code configured to enable the execution of;

receiving a first instruction for a data access operation, the first instruction being transmitted from a high-speed bus interface of a host device to a data cache; and

converting the first instruction into a second instruction compatible with at least one memory bank so as to perform the data access operation, the at least one memory bank being adapted for enabling high-speed data access.

16. The computer program product according to claim 15, wherein receiving the first instruction for the data access operation comprises:

receiving the first instruction from the high-speed bus interface of the host device via a high-speed bus interface switch; and

assigning the first instruction to a plurality of converters from the high-speed bus interface switch for the converting.

17. The computer program product according to claim 15, wherein the at least one memory bank comprises a plurality of memory banks, the method further comprising:

transmitting the second instruction to a buffer coupled to the plurality of memory banks; and

assigning the second instruction from the buffer to the plurality of memory banks.

18. The computer program product according to claim 17, wherein the first instruction is transmitted to the data cache from the high-speed bus interface of the host device through a host bus adapter.

19. The computer program product according to claim 15, wherein the high-speed bus interface comprises a peripheral component interface express (PCIe) bus interface.

20. The computer program product according to claim 15, wherein the memory bank comprises at least one double data rate (DDR) memory, and wherein the DDR memory comprises a non-volatile dual in-line memory module (NVDIMM).