Semiconductor Memory Having Volatile and Multi-Bit Non-Volatile Functionality and Method of Operating
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Abstract
A semiconductor memory cell, semiconductor memory devices comprising a plurality of the semiconductor memory cells, and methods of using the semiconductor memory cell and devices are described. A semiconductor memory cell includes a substrate having a first conductivity type; a first region embedded in the substrate at a first location of the substrate and having a second conductivity type; a second region embedded in the substrate at a second location of the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data in volatile memory; a trapping layer positioned in between the first and second locations and above a surface of the substrate; the trapping layer comprising first and second storage locations being configured to store data as nonvolatile memory independently of one another; and a control gate positioned above the trapping layer.
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Citations
40 Claims
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1-21. -21. (canceled)
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22. A semiconductor memory cell comprising:
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a substrate having a first conductivity type; a first region embedded in the substrate at a first location of the substrate and having a second conductivity type; a second region embedded in the substrate at a second location of the substrate and having the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data as volatile memory; a trapping layer positioned in between the first and second locations and above a surface of the substrate, the trapping layer comprising first and second storage locations configured to store data as nonvolatile memory independently of one another; and wherein said floating body is configured to be charged to a level indicative of a state of the memory cell based on charge stored in said one of said first and second storage locations in said trapping layer, upon restoration of power to said memory cell. - View Dependent Claims (23, 24, 25, 26, 27)
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28. A semiconductor memory cell comprising:
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a substrate having a first conductivity type; a first region embedded in the substrate at a first location of the substrate and having a second conductivity type; a second region embedded in the substrate at a second location of the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data as volatile memory; a trapping layer positioned in between the first and second locations and above a surface of the substrate, the trapping layer comprising first and second storage locations configured to store data as nonvolatile memory independently of one another; and wherein charge flow into said floating body upon restoration of power to said memory cell depends on charge stored in said one of said first and second storage locations in said trapping layer. - View Dependent Claims (29, 30, 31, 32, 33)
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34. A memory array comprising a plurality of rows and columns of semiconductor memory cells, a plurality of said cells each comprising:
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a floating body region to store charge as volatile memory; first and second regions; a trapping layer positioned in between the first and second locations and above a surface of the floating body region;
the trapping layer comprising first and second storage locations being configured to store charge as nonvolatile memory independently of one another;wherein said floating body region is configured to be charged to a level indicative of a state of the memory cell based on charge stored in said one of said first and second storage locations in said trapping layer, upon restoration of power to said memory cell. - View Dependent Claims (35, 36, 37, 38, 39, 40)
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Specification