MEMORY CIRCUIT HAVING NON-VOLATILE MEMORY CELL AND METHODS OF USING

• US 20160111168A1
• Filed: 10/19/2015
• Published: 04/21/2016
• Est. Priority Date: 10/17/2014
• Status: Active Grant

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Lattice Semiconductor Corporation
• Inventors: Cline, Ronald L., Logie, Stewart
• Granted Patent: US 9,672,935 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory

Abstract

One aspect relates to a memory circuit that has a programmable non-volatile memory (NVM) cell configured to generate an NVM output signal indicative of a program state of the NVM cell and to configure a volatile output based on the program state of the NVM cell. The NVM cell comprises a first anti-fuse device, a first select device connected in series with the first anti-fuse device at a first node, and a first pass device. The memory circuit also may have a programmable (independently of the NVM cell) volatile memory (VM) cell configured to receive the NVM output signal at a VM input node and to generate a VM output signal indicative of the program state of the VM cell. The NVM cell may have two NV elements that are separately programmable and are separately selectable via separate access transistors to drive the VM input node.

Claims

1. An article of manufacture comprising a memory circuit comprising:

volatile output circuitry (VOC); and

a programmable non-volatile memory (NVM) cell configured to generate an NVM output signal indicative of a program state of the NVM cell, the NVM cell comprising;

a first anti-fuse device;

a second anti-fuse device;

a first select device connected in series with the first anti-fuse device at a first node;

a second select device connected in series with the second anti-fuse device at a second node;

a first pass device connected between the first node and a VOC input node of the volatile output circuitry and usable to selectively pass a voltage at the first node to the VOC input node; and

a second pass device connected between the second node and the VOC input node and usable to selectively pass a voltage at the second node to the VOC input node, wherein the volatile output circuitry is connected to receive the NVM output signal from the NVM cell at the VOC input node and generate a VOC output signal indicative of the program state of the NVM cell.

2. The article of claim 1, wherein the VOC comprises a first inverter (e.g., INV1) comprising an input to receive the NVM output signal and to generate a first inverted signal at an output as the VOC output signal.

3. The article of claim 1, wherein the volatile output circuitry is an SRAM cell.

4. The article of claim 1, wherein:

the NVM cell is programmable to have a first programmed state by (i) turning off the first pass device and (ii) turning on the first select device to apply a programmable voltage level across a gate oxide layer of the first anti-fuse device to create a permanent breakdown path through the gate oxide layer of the first anti-fuse device;

the NVM cell is programmable to have a second programmed state different from the first programmed state by (i) turning off the second pass device and (ii) turning on the second select device to apply a programmable voltage level across a gate oxide layer of the second anti-fuse device to create a permanent breakdown path through the gate oxide layer of the second anti-fuse device; and

the volatile output circuitry is drivable using the NVM cell by (i) turning off the first and second select devices, (ii) applying read voltages to the first and second anti-fuse devices'"'"' gates, and (iii) turning on the first and second pass devices to pass a shorted voltage at the first and second nodes to the VOC input node.

5. The article of claim 4, wherein the volatile output circuitry is drivable by:

programming the NVM cell to have either the first or second programmed state; and

then driving the volatile output circuitry using the NVM cell such that;

if the NVM cell is programmed in the first programmed state, then the NVM output signal drives the volatile output circuitry based on the first programmed state; and

if the NVM cell is programmed in the second programmed state, then the NVM output signal drives the volatile output circuitry based on the second programmed state.

6. The article of claim 4, wherein the NVM cell in operation implements a programmable voltage divider wherein in the first programmed state, the shorted voltage is on one side of a common-mode voltage for the NVM cell and in the second programmed state, the shorted voltage is on the other side of the common-mode voltage for the NVM cell.

7. The article of claim 1, wherein:

the first and second select devices are controllable by a common program-enable control signal (e.g., PROG_EN); and

the first and second pass devices are controllable by a common transfer-enable control signal (e.g., LOAD).

8. The article of claim 1, wherein:

the first and second select devices are controllable by a common program-enable control signal; and

the first and second pass devices are controllable by independent transfer-enable control signals

9. The article of claim 1, wherein:

the first and second select devices are controllable by independent program-enable control signals; and

the first and second pass devices are controllable by a common transfer-enable control signal.

10. The article of claim 1, wherein the memory circuit is part of an integrated circuit comprising multiple instances of the memory circuit distributed over the integrated circuit, wherein, for each instance of the memory circuit, the NVM cell is co-located with the volatile output circuitry.

11. The article of claim 10, wherein the integrated circuit is a field-programmable gate array.

12. A method for operating a programmable Non-Volatile Memory (NVM) cell configured to generate an NVM output signal indicative of a program state of the NVM cell, the NVM cell comprising:

a first anti-fuse device;

a second anti-fuse device;

a first select device connected in series with the first anti-fuse device at a first node;

a second select device connected in series with the second anti-fuse device at a second node;

a first pass device connected between the first node and a NVM output node of the volatile output circuitry and usable to selectively pass a voltage at the first node to the NVM output node; and

a second pass device connected between the second node and the NVM output node and usable to selectively pass a voltage at the second node to the NVM output node, the method comprising reading a bit value from the NVM cell by;

turning off the first select device;

applying a read voltage to the first anti-fuse device'"'"'s gate; and

turning on the first pass device to pass a voltage at the first node to the NVM output node, wherein;

when the first anti-fuse device is blown, the voltage at the first node passed to the NVM output node will be at a first level; and

when the first anti-fuse device is not blown, the voltage at the first node passed to the NVM output node will be at a second level different from the first level

13. The method of claim 12, wherein:

turning off the first select device comprises turning off the first and the second select devices;

applying a read voltage to the first anti-fuse device'"'"'s gate comprises applying read voltages to the gates of the first and the second anti-fuse devices; and

turning on the first pass device comprises turning on the first and the second pass devices to pass a shorted voltage at the first and second nodes to the NVM output node, wherein;

if the first anti-fuse device is blown and the second anti-fuse device is not blown, the shorted voltage passed to the NVM output node will be at a first level; and

if the first anti-fuse device is not blown and the second anti-fuse device is blown, the shorted voltage passed to the NVM output node will be at a second level different from the first level.

14. The method of claim 13, wherein the NVM cell functions as a programmable voltage divider such that:

when the first anti-fuse device is blown and the second anti-fuse device is not blown, the shorted voltage is on one side of a common-mode voltage for the NVM cell and when the first anti-fuse device is not blown and the second anti-fuse device is blown, the shorted voltage is on the other side of the common-mode voltage for the NVM cell.

15. The method of claim 12, wherein the method further comprises reading an other bit value from the NVM cell by:

turning off the second select device;

applying a read voltage to the second anti-fuse device'"'"'s gate; and

turning on the second pass device to pass a voltage at the second node to the NVM output node, wherein;

if the second anti-fuse device is blown, then the voltage at the second node passed to the NVM output node will be at a third level; and

if the second anti-fuse device is not blown, then the voltage at the second node passed to the NVM output node will be at a fourth level different from the third level.

16. The method of claim 12, further comprising, prior to reading the bit value from the NVM cell, programming the bit value into the NVM cell by:

turning off the first pass device; and

turning on the first select device to apply a programmable voltage level across a gate oxide layer of the first anti-fuse device to create a permanent breakdown path through the gate oxide layer of the first anti-fuse device.

17. The method of claim 12, further comprising, prior to reading an other bit value from the NVM cell, programming the other bit value into the NVM cell by:

turning off the second pass device; and

turning on the second select device to apply a programmable voltage level across a gate oxide layer of the second anti-fuse device to create a permanent breakdown path through the gate oxide layer of the second anti-fuse device.

18. The method of claim 12, further comprising controlling the first and second select devices by a common program-enable control signal and controlling the first and second pass devices by a common transfer-enable control signal.

19. The method of claim 12, further comprising controlling the first and second select devices by a common program-enable control signal and controlling the first and second pass devices by separate and independent transfer-enable control signals.

20. The method of claim 12, further comprising controlling he first and second select devices are by independent program-enable control signals and controlling the first and second pass devices by a common transfer-enable control signal.

21. An article of manufacture comprising a memory circuit comprising:

a programmable non-volatile memory (NVM) cell configured to generate an NVM output signal indicative of a program state of the NVM cell, the NVM cell comprising a first anti-fuse device, a first select device connected in series with the first anti-fuse device at a first node, and a first pass device;

a programmable volatile memory (VM) cell configured to receive the NVM output signal at a VM input node and to generate a VM output signal indicative of the program state of the VM cell, wherein the first pass device is connected between the first node and the VM input node and usable to selectively pass a voltage at the first node to the VM input node, and control logic configured to (i) program the NVM cell by turning off the first pass device and turning on the first select device to apply a program voltage level across a gate oxide layer of the first anti-fuse device to create a permanent breakdown path through the gate oxide layer and to (ii) cause the VM cell to be configured by the programmed NVM cell by turning off the first select device, applying a read voltage to a gate of the first anti-fuse device, and turning on the first pass device to change the voltage at the VM input node using sufficient current flow through the gate oxide layer of the first anti-fuse device by an amount sufficient to flip the VM output signal.

22. The article of claim 21, wherein when the NVM cell is not programmed, (i) the first anti-fuse device is not blown, (ii) the NVM output signal is insufficiently definite for use in programming the VM cell, and (iii) the VM cell is programmable independent of the NVM output signal;

and when the NVM cell is programmed, (i) the first anti-fuse device is blown and (ii) the NVM output signal is sufficiently definite for use in programming the VM cell.

23. The article of claim 21, wherein the VM cell is configurable by pre-programming the VM cell to have a first programmed state independent of the NVM output signal;

and then configuring the VM cell using the NVM cell such that;

if the NVM cell is not programmed, then the NVM output signal does not change the VM cell from the first programmed state;

and if the NVM cell is programmed, then the NVM output signal does change the VM cell to a second programmed state different from the first programmed state.

24. The article of claim 21, wherein the memory circuit is part of an integrated circuit comprising multiple instances of the memory circuit distributed over the integrated circuit, wherein, for each instance of the memory circuit, the NVM cell is co-located with the VM cell.