3D NONVOLATILE MEMORY DEVICE

• US 20160111361A1
• Filed: 03/24/2015
• Published: 04/21/2016
• Est. Priority Date: 10/17/2014
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: OH, Sung Lae, KIM, Jin Ho
• Granted Patent: US 9,515,084 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/50 characterised by the boundary region between the core region and the peripheral circuit region
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

A 3D nonvolatile memory device including memory cells vertically stacked is disclosed. Word lines are integrally formed to be elongated over adjacent cell regions spaced apart from each other, and portions of the word lines between the cell regions are partially etched in a stepped shape to form word line contact regions.

Claims

1. A three-dimensional (3D) nonvolatile memory device comprising:

a first cell region;

a second cell region spaced apart from the first cell region; and

a stack of common word lines extending from the first cell region to the second cell region,

wherein the stack of common word lines includes N number of common word lines, where N is an integer.

2. The 3D nonvolatile memory device of claim 1, further comprising:

M number of pass transistors located under the stack of common word lines, and configured to supply programming voltages to the stack of common word lines based on a block selection signal, where M is an integer.

3. The 3D nonvolatile memory device of claim 2,

wherein each of the pass transistors include a gate, a first junction region and a second junction region, wherein the first and second junction regions are formed at first and second sides of the gate, respectively, such that the first junction region is located in a slit region and the first junction region is provided between the stack of common word lines and a neighboring stack of common word lines.

4. The 3D nonvolatile memory device of claim 3, further comprising:

a first contact located in the slit region and configured to electrically couple the first junction region to the L^th common word line, where L is an integer and 1≦

L≦

N.

5. The 3D nonvolatile memory device of claim 1,

wherein the stack of common word lines includes a first slim region in which X number of common word lines are exposed in the first slim region, and the X number of common word lines form a stepped structure in the first slim region, where X is an integer and 1≦

X≦

N.

6. The 3D nonvolatile memory device of claim 5,

wherein the first slim region is located between the first cell region and the second cell region, and the stack of common word lines extends from the first cell region through the first slim region to the second cell region.

7. The 3D nonvolatile memory device of claim 6, wherein the stack of common word lines further includes a second slim region,

wherein the first slim region is located at a first sidewall of the stack of common word lines,

wherein the second slim region is located at a second sidewall of the stack of common word lines, and

wherein the second sidewall is located opposite to the first sidewall.

8. The 3D nonvolatile memory device of claim 7,

wherein the first slim region is located closer to the first cell region than the second cell region, and

wherein the second slim region is located between the first cell region and the second cell region, and is closer to the second cell region than the first cell region.

9. The 3D nonvolatile memory device of claim 7,

wherein Y number of common word lines are exposed in the second slim region, and the Y number of common word lines form a stepped structure in the second slim region, where Y is an integer and 1≦

X≦

N.

10. The 3D nonvolatile memory device of claim 9,

wherein N−

X=Y, and each of the X number of common word lines and each of the Y number of common word lines are different from each other.

11. The 3D nonvolatile memory device of claim 6,

wherein the first slim region is located in a first sidewall of the stack of common word lines, and the first slim region includes a plurality of slim regions.

12. The 3D nonvolatile memory device of claim 1,

wherein the stack of common word lines includes E number of slim regions,

wherein the N number common word lines are divided into the E number of groups, and

wherein the E number of groups correspond to the E number of slim regions, respectively, and are exposed by their respective slim regions, where E is an integer and 1≦

E≦

N.

13. A method of fabricating a three-dimensional (3D) nonvolatile memory device, the method comprising:

forming a stack structure including N number of conductive layers, formed over a semiconductor substrate, wherein the semiconductor substrate includes a first cell region, a second cell region spaced apart from the first cell region, and a pass transistor region between the first cell region and the second cell region, wherein the stack structure extends from the first cell region through the pass transistor region to the second cell region, where N is an integer;

forming an etch stop layer over the stack structure;

defining a slim region by removing the etch stop layer located in the pass transistor region;

forming a photoresist pattern over the slim region and the etch stop layer to expose a first region of the N^th conductive layer in the slim region;

performing selective primary etching against the exposed first region of the N^th conductive layer using the photoresist pattern to expose a first region of the N−

1^th conductive layer;

slimming the photoresist pattern to expose a second region of the N^th conductive layer; and

performing secondary etching against the exposed first region of the N−

1^th conductive layer and the exposed second region of the N^th conductive layer using the slimmed photoresist pattern to expose a first region of the N−

2^th conductive layer and to exposed a second region of the N−

1^th conductive layer, respectively,

wherein the second region of the N−

1^th conductive layer, and the first region of the N−

2^th conductive layer form a stepped structure in the slim region, where N is an integer.

14. The method of claim 13, further comprising:

performing breakthrough etching between the primary etching and the secondary etching.

15. The method of claim 13,

wherein, upon completion of the slimming process, the first region of the N−

1^th conductive layer and the second region of the N^th conductive layer form a stepped structure in the slim region.

16. The method of claim 13, further comprising:

slimming the photoresist pattern to expose a third region of the N^th conductive layer,

wherein the third region of the N^th conductive layer, the second region of the N−

1^th conductive layer, and the first region of the N−

2^th conductive layer form a stepped structure in the slim region.