THREE-DIMENSIONAL MEMORY STRUCTURE HAVING SELF-ALIGNED DRAIN REGIONS AND METHODS OF MAKING THEREOF

• US 20160111435A1
• Filed: 12/21/2015
• Published: 04/21/2016
• Est. Priority Date: 10/15/2014
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Pang, Liang, Pachamuthu, Jayavel, Dong, Yingda
• Granted Patent: US 9,543,320 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/2236 from or into a plasma phase
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

A memory stack structure can be formed through a stack of an alternating plurality of first material layers and second material layers and through an overlying temporary material layer having a different composition than the first and second material layers. The memory stack structure can include a memory film and a semiconductor channel layer. The overlying temporary material layer is removed selective to the stack to form a lateral recess. Portions of the memory film are removed around the lateral recess, and dopants are laterally introduced into an upper portion of the semiconductor channel to form a self-aligned drain region.

Claims

1. A method of manufacturing a three-dimensional memory structure, comprising:

forming a stack of alternating layers comprising first material layers and second material layers over a substrate;

forming a temporary material layer over the stack;

wherein the temporary material layer has a different composition than the first material layers and second material layers;

forming a memory opening through the temporary material layer and the stack;

forming a memory film and a semiconductor channel in the memory opening;

forming a first backside recess by removing the temporary material layer and a portion of the memory film that adjoins the temporary material layer, wherein a portion of a sidewall of the semiconductor channel is physically exposed to the first backside recess; and

introducing electrical dopants through the physically exposed portion of the sidewall of the semiconductor channel and into a portion of the semiconductor channel, which is converted into a drain region.

2. The method of claim 1, further comprising:

forming a trench through the temporary material layer and the stack; and

removing a material of the temporary material layer selective to materials of the first and second material layers to form second backside recesses.

3. The method of claim 2, further comprising simultaneously filling the first and second backside recesses with a combination of a dielectric liner and a conductive material.

4. The method of claim 3, wherein the first backside recess is formed prior to formation of the second backside recesses.

5. The method of claim 3, wherein the dielectric liner is formed on a sidewall of the drain region at a level of the temporary material layer, and on a sidewall of the memory film at each level of the second material layer.

6. The method of claim 3, wherein the dielectric liner is formed on a top surface of a remaining portion of the memory film, and on a bottom surface of another remaining portion of the memory film.

7. The method of claim 1, wherein the portion of the semiconductor channel is doped with the electrical dopants by a plasma doping process.

8. The method of claim 1, wherein the temporary material layer comprises a semiconductor material and the second material layers comprise a dielectric material.

9. The method of claim 1, wherein the temporary material layer is formed between an underlying dielectric material layer and an overlying dielectric material layer, and the portion of the memory film that adjoins the temporary material layer is isotropically etched to expand the first backside recess above a horizontal plane including a bottom surface of the overlying dielectric material layer and below another horizontal plane including a top surface of the underlying dielectric material layer.

10. The method of claim 1, further comprising forming a contact via structure that extends partially into the memory opening and contacting a top surface of the drain region.

11. The method of claim 10, wherein the contact via structure is formed on an inner sidewall of the drain region.

12. The method of claim 1, further comprising:

forming a device over the substrate, wherein the device comprises a vertical NAND device located in a device region; and

forming at least one electrically conductive layer in the stack that comprises, or is electrically connected to, a word line of the NAND device.

13. The method of claim 12, wherein:

the substrate comprises a silicon substrate;

the NAND device comprises array of monolithic three dimensional NAND strings over the silicon substrate;

at least one memory cell in the first device level of the three dimensional array of NAND strings is located over another memory cell in the second device level of the three dimensional array of NAND strings;

the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon; and

each NAND string comprises;

a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the semiconductor substrate;

a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels; and

a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level.