BATCH CONTACTS FOR MULTIPLE ELECTRICALLY CONDUCTIVE LAYERS

• US 20160111438A1
• Filed: 10/20/2014
• Published: 04/21/2016
• Est. Priority Date: 10/20/2014
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: TSUTSUMI, Masanori, Yada, Shinsuke, Honma, Ryoichi, Ihata, Naoki
• Granted Patent: US 9,530,787 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

A stepped structure is formed on a stack of an alternating plurality of insulator layers and material layers such that at least two material layers have vertically coincident sidewalls. In one embodiment, the material layers can be electrically conductive layers, and a contact via structure can contact the vertically coincident sidewalls. In another embodiment, a sacrificial spacer can be formed on the vertically coincident sidewalls, and the material layers and the sacrificial spacer can be replaced with a conductive material. A contact via structure can be formed on a set of layers electrically shorted by a vertical conductive material portion that is formed in a volume of the spacer. The contact via structure can provide electrical contact to multiple electrically conductive layers.

Claims

1. A multilevel structure, comprising:

a stack of an alternating plurality of electrically conductive layers and insulator layers located over a substrate;

a plurality of contact via structures having bottom surfaces contacting a respective electrically conductive layer located at different levels; and

a vertically extending conductive material portion contacting at least two electrically conductive layers and contacting each sidewall of at least one intervening insulator layer that is located between a topmost electrically conductive layer among the at least two electrically conductive layers and a bottommost electrically conductive layer among the at least two electrically conductive layers.

2. The multilevel structure of claim 1, wherein the at least one intervening insulator layer comprises a plurality of intervening insulator layers having sidewalls that are vertically coincident among one another.

3. The multilevel structure of claim 1, wherein the vertically extending conductive material portion is a portion within one of the plurality of contact via structures.

4. The multilevel structure of claim 3, wherein the vertically extending conductive material portion contacts a top surface of the bottommost electrically conductive layer among the at least two electrically conductive layers.

5. The multilevel structure of claim 3, wherein at least one insulator layer is located between the topmost electrically conductive layer among the at least two electrically conductive layers and the bottommost electrically conductive layer among the at least two electrically conductive layers, and has a sidewall surface that is vertically coincident with a sidewall of the topmost electrically conductive layer among the at least two electrically conductive layers.

6. The multilevel structure of claim 3, wherein the at least two electrically conductive layers comprises at least three electrically conductive layers, and the sidewall of the at least one insulator layer is vertically coincident with a sidewall of an electrically conductive layer that is located between the topmost and bottommost electrically conductive layers among the at least three electrically conducting layers.

7. The multilevel structure of claim 3, wherein the vertically extending conductive material portion contacts a sidewall of each electrically conductive layer within the at least two electrically conductive layers.

8. The multilevel structure of claim 1, wherein the vertically extending conductive material portion is a conductive material spacer having a same composition with the electrically conductive layers within the stack.

9. The multilevel structure of claim 8, wherein the conductive material spacer is of integral construction with an entirety of the at least two electrically conductive layers.

10. The multilevel structure of claim 8, wherein a portion of the electrically conductive via contacts a top surface of the topmost electrically conductive layer among the at least two electrically conductive layers.

11. The multilevel structure of claim 8, wherein the vertically extending conductive material portion is of integral construction with the at least two electrically conductive layers without any interface between the vertically extending conductive material portion and the at least two electrically conductive layers.

12. The multilevel structure of claim 8, further comprising:

a stepped dielectric material portion located on the substrate; and

a spacer located on the stepped dielectric material portion and having a same thickness as, and having a different composition from, the vertically extending conductive material portion.

13. The multilevel structure of claim 1, wherein the multilevel structure comprises at least one memory stack structure embedded within the stack, and a subset of the electrically conductive layers comprises control gate electrodes for the at least one memory stack structure, and the at least two electrically conductive layers comprise select gate electrodes located above, or underneath, the control gate electrodes.

14. The multilevel structure of claim 13, further comprising:

control gate contact via structures contacting, and vertically extending above, a respective electrically conductive layer within the subset of electrically conductive layers;

a select gate contact via structure contacting the at least two electrically conductive layers and having a greater lateral extent along a horizontal direction than a maximum lateral extent of any of the control gate contact via structures along the horizontal direction.

15. The multilevel structure of claim 1, further comprising a second vertically extending conductive material portion contacting at least two additional electrically conductive layers and contacting each sidewall of at least one additional intervening insulator layer that is located between a topmost electrically conductive layer among the at least two additional electrically conductive layers and a bottommost electrically conductive layer among the at least two additional electrically conductive layers, wherein:

a subset of the electrically conductive layers comprises control gate electrodes for the at least one memory stack structure;

the at least two electrically conductive layers comprise upper select gate electrodes located above the control gate electrodes; and

the at least two additional electrically conductive layers comprise lower select gate electrodes located below the control gate electrodes.

16. The multilevel structure of claim 15, wherein:

the multilevel structure comprises a vertical NAND device is located over the substrate; and

the electrically conductive layers comprise, or are electrically connected to a respective word line of the NAND device.

17. The semiconductor structure of claim 16, wherein:

the substrate comprises a silicon substrate;

the NAND device comprises an array of monolithic three dimensional NAND strings over the silicon substrate;

at least one memory cell in the first device level of the three dimensional array of NAND strings is located over another memory cell in the second device level of the three dimensional array of NAND strings;

the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon; and

each NAND string comprises;

a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the semiconductor substrate;

a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels; and

a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level.

18. A method of fabricating a multilevel structure, comprising:

forming a stack comprising an alternating plurality of sacrificial material layers and insulator layers over a substrate;

patterning the stack to form a stepped structure in which each overlying layer in the stack does not protrude more than any underlying layer in the stack; and

forming a contact via structure directly on surfaces of at least two electrically conductive layers within the stack.

19. The method of claim 18, further comprising forming a dielectric material portion having a planar top surface over the stepped structure, wherein the contact via structure is formed through the dielectric material portion.

20. The method of claim 18, wherein a bottom surface of the contact via structure is formed directly on a top surface of a bottommost electrically conductive layer among the at least two electrically conductive layers.

21. The method of claim 18, wherein the contact via structure contacts a sidewall of each electrically conductive layer within the at least two electrically conductive layers.

22. The method of claim 18, wherein:

at least one intervening insulator layer located between a topmost and bottommost electrically conductive layers within the at least two electrically conductive layers; and

each of the at least one intervening insulator layer has a sidewall that is vertically coincident with sidewalls of the at least two electrically conductive layers.

23. The method of claim 18, further comprising forming at least one memory stack structure within the stack, wherein a subset of the electrically conductive layers comprises control gate electrodes for the at least one memory stack structure, and the at least two electrically conductive layers comprise select gate electrodes located above, or underneath, the control gate electrodes.

24. The method of claim 23, further comprising:

forming control gate contact via structures on a top surface of a respective electrically conductive layer within the subset of electrically conductive layers, wherein;

the contact via structure has a greater lateral extent along a horizontal direction than a maximum lateral extent of any of the control gate contact via structures along the horizontal direction.

25. The method of claim 18, further comprising forming a device on the substrate, wherein:

the device comprises a vertical NAND device; and

at least one of the electrically conductive layers in the stack comprises, or is electrically connected to, a word line of the vertical NAND device.

26. The method of claim 25, wherein:

the NAND device comprises;

a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the semiconductor substrate;

a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels; and

a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate;

the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level;

the electrically conductive layers in the stack comprise, or are in electrical contact with, the plurality of control gate electrodes and extends from the device region to a contact region containing the plurality of electrically conductive via connections; and

the substrate comprises a silicon substrate containing a driver circuit for the NAND device.

27. A method of fabricating a multilevel structure, comprising:

forming a stack comprising an alternating plurality of sacrificial material layers and insulator layers over a substrate;

patterning the stack to form a stepped structure in which each overlying layer in the stack does not protrude more than any underlying layer in the stack, wherein at least two sacrificial material layers have vertically coincident sidewalls after formation of the stepped structure;

forming a sacrificial spacer on the vertically coincident sidewalls of the at least two sacrificial material layers; and

replacing the materials of the sacrificial material layers and the sacrificial spacer with a conductive material, whereby electrically conductive layers are formed in volumes of the sacrificial material layers and a conductive material spacer is formed in a volume of the sacrificial spacer.

28. The method of claim 27, wherein at least two of the electrically conductive layers that are formed within volumes of the at least two sacrificial material layers have sidewalls that are vertically coincident among one another, and contact the conductive material spacer.

29. The method of claim 27, further comprising forming a dielectric material portion having a planar top surface over the stepped structure after formation of the sacrificial spacer.

30. The method of claim 29, further comprising forming a contact via structure through the dielectric material portion to at least two electrically conductive layers that are formed within volumes of the at least two sacrificial material layers.

31. The method of claim 30, wherein a bottom surface of the contact via structure is formed directly on a topmost electrically conductive layer among the at least two electrically conductive layers.

32. The method of claim 27, further comprising forming at least one memory stack structure within the stack, wherein a subset of the electrically conductive layers comprises control gate electrodes for the at least one memory stack structure, and the at least two electrically conductive layers comprise select gate electrodes located above, or underneath, the control gate electrodes.

33. The method of claim 32, further comprising:

forming control gate contact via structures on a top surface of a respective electrically conductive layer within the subset of electrically conductive layers, wherein;

the contact via structure has a greater lateral extent along a horizontal direction than a maximum lateral extent of any of the control gate contact via structures along the horizontal direction.

34. The method of claim 27, further comprising forming a device on the substrate, wherein:

the device comprises a vertical NAND device; and

at least one of the electrically conductive layers in the stack comprises, or is electrically connected to, a word line of the vertical NAND device.

35. The method of claim 34, wherein:

the NAND device comprises;

a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the semiconductor substrate;

a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels; and

a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate;

the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level;

the electrically conductive layers in the stack comprise, or are in electrical contact with, the plurality of control gate electrodes and extends from the device region to a contact region containing the plurality of electrically conductive via connections; and

the substrate comprises a silicon substrate containing a driver circuit for the NAND device.