INTEGRATED CIRCUITS WITH LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR STRUCTURES AND METHODS FOR FABRICATING THE SAME

• US 20160111488A1
• Filed: 10/20/2014
• Published: 04/21/2016
• Est. Priority Date: 10/20/2014
• Status: Active Grant

• Current Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Original Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Inventors: Lu, Yi, Wang, Dongli, Verma, Purakh Raj, Chen, Deyan
• Granted Patent: US 9,842,903 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76229 Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66704 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236

Abstract

Integrated circuits with improved laterally diffused metal oxide semiconductor (LDMOS) structures, and methods of fabricating the same, are provided. An exemplary LDMOS integrated circuit includes an n-type reduced surface field, a p-type body well disposed on a lateral side of the n-type reduced surface field region, a shallow trench isolation structure disposed within the n-type reduced surface field region, and a gate structure disposed partially over the p-type body well, partially over the n-type reduced surface field region, partially over the shallow trench isolation structure, and partially within the shallow trench isolation structure.

Claims

1. A laterally diffused metal oxide semiconductor (LDMOS) integrated circuit structure comprising:

an n-type reduced surface field region;

a p-type body well disposed on a lateral side of the n-type reduced surface field region;

a shallow trench isolation structure disposed within the n-type reduced surface field region; and

a gate structure disposed partially over the p-type body well, partially over the n-type reduced surface field region, partially over the shallow trench isolation structure, and partially within the shallow trench isolation structure.

2. The LDMOS integrated circuit structure of claim 1, wherein the shallow trench isolation structure comprises at least one silicon oxide layer and at least one silicon nitride layer.

3. The LDMOS integrated circuit structure of claim 2, wherein the shallow trench isolation structure comprises first and second silicon oxide layers separated by the at least one silicon nitride layer.

4. The LDMOS integrated circuit structure of claim 3, wherein the gate structure extends into the shallow isolation trench structure below an upper surface defined by the p-type body well and the n-type reduced surface field region.

5. The LDMOS integrated circuit structure of claim 4, wherein the gate structure extends into the shallow trench isolation structure through the second silicon oxide layer to contact with the silicon nitride layer, but does not extend through the silicon nitride layer.

6. The LDMOS integrated circuit structure of claim 5, wherein the gate structure extends within the shallow trench isolation structure in an area proximate a source side of the shallow trench isolation structure that is adjacent to the p-type body well.

7. The LDMOS integrated circuit structure of claim 1, further comprising an N+ source region disposed within the p-type body well.

8. The LDMOS of integrated circuit structure of claim 1, further comprising an N+ drain region disposed within the n-type reduced surface field region.

9. The LDMOS integrated circuit structure of claim 1, further comprising a P+ body contact region disposed within the p-type body well.

10. The LDMOS integrated circuit structure of claim 1, further comprising an n-type deep well region, wherein the n-type reduced surface field region is disposed over and in contact with the n-type deep well region.

11. The LDMOS integrated circuit structure of claim 10, further comprising a p-type isolation well disposed on a lateral side of the n-type deep well region.

12. The LDMOS integrated circuit structure of claim 11, further comprising a P+ contact region disposed within the p-type isolation well.

13. The LDMOS integrated circuit structure of claim 1, further comprising a second shallow trench isolation structure disposed adjacent to the p-type body well.

14. The LDMOS integrated circuit structure of claim 1, further comprising a p-type semiconductor substrate, wherein the n-type deep well region is disposed over and in contact with the p-type semiconductor substrate.

15. A method for forming an LDMOS integrated circuit comprising:

forming an n-type reduced surface field region and a p-type body well in a semiconductor substrate, wherein the p-type body well is disposed on a lateral side of the n-type reduced surface field region;

forming a first trench within the n-type reduced surface field region;

forming a shallow trench isolation structure within the trench;

forming a second trench within the shallow trench isolation structure; and

forming a gate structure over the n-type reduced surface field region, over the p-type body well, over the shallow trench isolation structure, and within the second trench.

16. The method of claim 15, wherein forming the shallow trench isolation structure comprises depositing a first silicon oxide dielectric layer in the trench, depositing a silicon nitride layer over the first silicon oxide dielectric layer, and depositing a second silicon oxide dielectric layer over the silicon nitride layer.

17. The method of claim 16, wherein forming the second trench comprises etching the shallow trench isolation structure through the second silicon oxide dielectric layer and stopping at the silicon nitride layer.

18. The method of claim 16, wherein forming the second trench comprises etching the shallow trench isolation structure at a source end thereof proximate the p-type body well.

19. The method of claim 15, wherein forming the gate structure comprises depositing a polycrystalline silicon material within the second trench.

20. A laterally diffused metal oxide semiconductor (LDMOS) integrated circuit structure comprising:

a p-type semiconductor substrate;

an n-type deep well region disposed over and in contact with the p-type semiconductor substrate;

an n-type reduced surface field region disposed over and in contact with the n-type deep well region;

a p-type body well disposed on a lateral side of the n-type reduced surface field region;

a shallow trench isolation structure disposed within the n-type reduced surface field region; and

a gate structure disposed partially over the p-type body well, partially over the n-type reduced surface field region, partially over the shallow trench isolation structure, and partially within the shallow trench isolation structure,

wherein the shallow trench isolation structure comprises first and second silicon oxide layers separated by the at least one silicon nitride layer,

wherein the gate structure extends into the shallow isolation trench structure below an upper surface defined by the p-type body well and the n-type reduced surface field region, and

wherein the gate structure extends into the shallow trench isolation structure through the second silicon oxide layer to contact with the silicon nitride layer, but does not extend through the silicon nitride layer.