Semiconductor Devices Including Channel Regions with Varying Widths

• US 20160111531A1
• Filed: 05/27/2015
• Published: 04/21/2016
• Est. Priority Date: 10/16/2014
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Dong, Yaoqi
• Application Number:
  US14/723,137
• Publication Number:
  US 20160111531A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor device includes a semiconductor substrate, a fin-type structure on the semiconductor substrate, and a gate on a portion of a top surface and portions of two side surfaces of the fin-type structure. The gate has a first width at a first level from the top surface of the substrate and a second width at a second level from the top surface of the substrate that is lower than the first level. The first width is greater than the second width, and a width of the gate is reduced from the first width to the second width between the first level and the second level.

Claims

1. A semiconductor device comprising:

a semiconductor substrate having an upper surface;

a fin-type structure on the semiconductor substrate, the fin-type structure having a top surface opposite the substrate and two opposing side surfaces; and

a gate on a portion of the top surface and portions of the two side surfaces of the fin-type structure;

wherein the gate has a first width at a first level from the upper surface of the substrate and a second width at a second level from the upper surface of the substrate,

wherein the second level is lower than the first level,

wherein the first width is greater than the second width, and

wherein a width of the gate is reduced from the first width to the second width between the first level and the second level.

2. The device of claim 1, wherein the width of the gate is reduced with a constant rate of change from the first width to the second width between the first level and the second level.

3. The device of claim 1, wherein the width of the gate is reduced with at least two rates of change from the first width to the second width between the first level and the second level.

4. The device of claim 1, wherein the width of the gate is reduced at a continuously varying rate of change from the first width to the second width between the first level and the second level.

5. The device of claim 1, wherein the first level is at substantially the same level as a top surface of the gate.

6. The device of claim 1, wherein the first level is at a lower level than a top surface of the gate.

7. The device of claim 1, further comprising an insulating layer formed on the semiconductor substrate to have a top surface that is at a lower level than a top surface of the fin-type structure, wherein the second level is at substantially the same level as the top surface of the insulating layer.

8. The device of claim 1, farther comprising an insulating layer formed on the semiconductor substrate to have a top surface that is at a lower level than a top surface of the fin-type structure, wherein the second level is at an upper level than the top surface of the insulating layer.

9. The device of claim 1, wherein a third width of the gate at a third level that is lower than the second level is equal to or larger than the second width.

10. The device of claim 1, wherein a third width of the gate at a third level that is lower than the first level is equal to or smaller than the first width.

11. The device of claim 1, wherein on side surfaces of the fin-type structure, a source region and a drain region are formed on the fin-type structure on two sides of the gate, wherein a first resistance between the source region and the drain region on the two sides of the gate at the first level is greater than a second resistance between the source region and the drain region on the two sides of the gate at the second level.

12. The device of claim 1, wherein the fin-type structure protrudes from the substrate, and the insulating layer defines the fin-type structure.

13. The device of claim 1, wherein the fin-type structure is formed on the insulating layer.

14. A semiconductor device comprising:

a semiconductor substrate;

a fin-type structure on the semiconductor substrate;

an insulating layer formed on the semiconductor substrate to have a top surface that is at lower level than a top surface of the fin-type structure; and

a gate on a portion of a top surface of the fin-type structure and portions of side surfaces of the fin-type structure,

wherein a width of the gate is reduced from a first width at an upper portion of the fin-type structure to a second width at a lower portion of the fin-type structure.

15. The device of claim 14, wherein, in a range, the gate includes a first side and a second side that extend from an upper portion of the fin-type structure toward a lower portion thereof, the first side of the gate extends in a first direction, and the second side of the gate extends in a second direction that is inclined at a different angle from the first direction with respect to a direction vertical to the insulating layer.

16. A semiconductor device, comprising:

a semiconductor substrate having an upper surface;

a fin on the semiconductor substrate, the fin having an upper portion distal from the substrate and a lower portion proximate the substrate, and including a source region and a drain region in opposite ends of the fin and a channel region between the source region and the drain region;

a gate on the channel region and extending down a side of the fin from a top of the fin towards a bottom of the fin between the source region and the drain region;

a source contact on an upper surface of the fin in the source region; and

a drain contact on an upper surface of the fin in the drain region,

wherein the gate has a first width at the upper portion of the fin and a second width at the lower portion of the fin, the first width being greater than the second width.

17. The device of claim 16, wherein the width of the gate has a constant rate of change from the first width to the second width.

18. The device of claim 16, wherein the width of the gate is reduced with at least two rates of change from the first width to the second width.

19. The device of claim 16, wherein the width of the gate is reduced at a continuously varying rate of change from the first width to the second width.

20. The device of claim 16, wherein the gate has a third width at a portion of the fin beneath the second width, the third width being greater than the second width.