OPTOELECTRONIC DEVICE INCLUDING IMPROVED THERMAL MANAGEMENT

• US 20160111618A1
• Filed: 05/07/2015
• Published: 04/21/2016
• Est. Priority Date: 05/07/2014
• Status: Abandoned Application

• Current Assignee: Sensor Electronic Technology Incorporated (Seoul Semiconductor Co., Ltd.)
• Original Assignee: Sensor Electronic Technology Incorporated (Seoul Semiconductor Co., Ltd.)
• Inventors: Shur, Michael, Shatalov, Maxim S., Dobrinsky, Alexander, Gaska, Remigijus
• Application Number:
  US14/706,141
• Publication Number:
  US 20160111618A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/00 Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor H01L31/00 - H01L33/00, H10K10/00, H10N take precedence; details other than of semiconductor bodies or of electrodes thereof H01L23/00; devices consisting of a plurality of solid state components formed in or on a common substrate H01L27/00
• CPC Class Codes: H01L 33/005 Processes
• CPC Class Codes: H01L 33/02 characterised by the semiconductor bodies
• CPC Class Codes: H01L 33/641 characterized by the materials

Abstract

A heterostructure for use in fabricating an optoelectronic device with improved thermal management is provided. The heterostructure can include a plurality of epitaxially grown layers including an n-type contact layer, an active layer, and a p-type contact layer. N-type and p-type electrodes for the n-type contact layer and p-type contact layer, respectively, can be embedded within an electrically insulating, thermally conductive semiconductor layer that is adjacent to the epitaxially grown layers. The electrically insulating, thermally conductive semiconductor layer can provide a larger lateral area for extracting heat generated by the active layer, so that there is improved thermal management within the device.

Claims

1. A heterostructure comprising:

a plurality of epitaxially grown layers, including;

an n-type contact layer; and

a mesa region adjacent to the n-type contact layer, the mesa region comprising an active layer and a p-type contact layer;

an n-type electrode to the n-type contact layer;

a p-type electrode to the p-type contact layer; and

an electrically insulating, thermally conductive semiconductor layer adjacent to the mesa region, wherein a thermal conductivity of the electrically insulating, thermally conductive semiconductor layer is at least five percent of the thermal conductivity of at least one of the plurality of epitaxially grown layers.

2. The heterostructure of claim 1, wherein the p-type electrode and the n-type electrode are embedded within the electrically insulating, thermally conductive semiconductor layer.

3. The heterostructure of claim 2, wherein the electrically insulating, thermally conductive semiconductor layer is electrically conductive.

4. The heterostructure of claim 3, further comprising a set of insulating materials located between the p-type electrode and the electrically insulating, thermally conductive semiconductor layer and the n-type electrode and the electrically insulating, thermally conductive semiconductor layer.

5. The heterostructure of claim 1, further comprising an interface layer located between the p-type contact layer of the mesa region and the electrically insulating, thermally conductive semiconductor layer.

6. The heterostructure of claim 1, further comprising a set of thermally conductive fillers within the electrically insulating, thermally conductive semiconductor layer.

7. The heterostructure of claim 1, further comprising a submount for mounting the heterostructure to fabricate an optoelectronic device, wherein the optoelectronic device is located within a package.

8. The heterostructure of claim 7, wherein the package is placed within a cavity of a heat sink for extracting heat generated from the optoelectronic device.

9. The heterostructure of claim 7, wherein the electrically insulating, thermally conductive semiconductor layer is located between the heterostructure and the package.

10. The heterostructure of claim 9, wherein the electrically insulating, thermally conductive semiconductor layer includes a plurality of thermally conductive nanoparticles.

11. An optoelectronic device, comprising:

a plurality of epitaxially grown layers, including;

a substrate;

an n-type contact layer to the substrate; and

a mesa region adjacent to the n-type contact layer, the mesa region comprising an active layer and a p-type contact layer;

an n-type electrode to the n-type contact layer;

a p-type electrode to the p-type contact layer; and

an electrically insulating, thermally conductive semiconductor layer adjacent to the mesa region, wherein a thermal conductivity of the electrically insulating, thermally conductive semiconductor layer is at least five percent of thermal conductivity of at least one of the plurality of epitaxially grown layers.

12. The device of claim 11, wherein the p-type electrode and the n-type electrode are embedded within the electrically insulating, thermally conductive semiconductor layer.

13. The device of claim 12, wherein the electrically insulating, thermally conductive semiconductor layer is electrically conductive.

14. The device of claim 13, further comprising a set of insulating materials located between the p-type electrode and the electrically insulating, thermally conductive semiconductor layer and the n-type electrode and the electrically insulating, thermally conductive semiconductor layer.

15. The device of claim 11, further comprising an interface layer located between the p-type contact layer of the mesa region and the electrically insulating, thermally conductive semiconductor layer.

16. The device of claim 11, further comprising a set of thermally conductive fillers within the electrically insulating, thermally conductive semiconductor layer.

17. A method of fabricating a device, the method comprising:

epitaxially growing a plurality of layers on a substrate, wherein the plurality of layers includes;

a substrate;

an n-type contact layer to the substrate;

a mesa region adjacent to the n-type contact layer, the mesa region comprising an active layer and a p-type contact layer; and

an electrically insulating, thermally conductive semiconductor layer adjacent to the mesa region, wherein a thermal conductivity of the electrically insulating, thermally conductive semiconductor layer is at least five percent of the thermal conductivity of at least one of the plurality of epitaxially grown layer.

18. The method of claim 17, further comprising:

etching a first portion of the plurality of layers to expose the n-type contact layer; and

forming an n-type electrode for contact to the n-type contact layer.

19. The method of claim 18, further comprising:

etching a second portion of the plurality of layers to expose the p-type contact layer; and

forming a p-type electrode for contact to the p-type contact layer.

20. The method of claim 19, further comprising epitaxially growing the plurality of layers includes epitaxially growing an interface layer between the mesa region and the electrically insulating, thermally conductive semiconductor layer.