INTEGRATED CIRCUIT CAPACITORS FOR ANALOG MICROCIRCUITS

• US 20160112011A1
• Filed: 12/31/2015
• Published: 04/21/2016
• Est. Priority Date: 03/19/2014
• Status: Active Grant

• Current Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Original Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Inventors: Kumar, Vinod
• Granted Patent: US 9,813,024 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G05F 3/16 being semiconductor devices
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 29/66181 Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/94 Metal-insulator-semiconductors, e.g. MOS
• CPC Class Codes: H03F 1/0205 in transistor amplifiers
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 3/193 with field-effect devices H03F3/195 takes precedence
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence

Abstract

Dual gate FD-SOI transistors are used as MOSFET capacitors to replace passive well capacitors in analog microcircuits. Use of the dual gate FD-SOI devices helps to reduce unstable oscillations and improve circuit performance. A thick buried oxide layer within the substrate of an FD-SOI transistor forms a capacitive dielectric that can sustain high operating voltages in the range of 1.2 V-3.3 V, above the transistor threshold voltage. A secondary gate in the FD-SOI transistor is used to create a channel from the back side so that even when the bias voltage on the first gate is small, the effective capacitance remains higher. The capacitance of the buried oxide layer is further utilized as a decoupling capacitor between supply and ground. In one example, a dual gate PMOS FD-SOI transistor is coupled to an operational amplifier and a high voltage output driver to produce a precision-controlled voltage reference generator. In another example, two dual gate PMOS and one dual gate NMOS FD-SOI transistor are coupled to a charge pump, a phase frequency detector, and a current-controlled oscillator to produce a high-performance phase locked loop circuit in which the decoupling capacitor footprint is smaller, in comparison to the conventional usage of passive well capacitance.

Claims

1. A method, comprising:

forming a capacitive dual gate field effect transistor in an active layer of a silicon-on-insulator (SOI) substrate having a buried oxide layer overlying a doped region, the capacitive transistor including source and drain regions having substantially vertical profiles that are oriented perpendicular to the buried oxide layer; and

forming a front side contact to the doped region of the transistor.

2. The method of claim 1 wherein the doped region is an N-well and the transistor is a p-type device.

3. The method of claim 1 wherein the doped region is a P-well and the transistor is an n-type device.

4. The method of claim 1, further comprising:

forming an interconnect that couples the source and drain regions to a power supply; and

forming an interconnect that couples the doped region to ground.

5. The method of claim 1 wherein forming the capacitive dual gate field effect transistor further comprises

forming, as a first capacitive dielectric, a primary gate oxide layer that is substantially thinner than the buried oxide layer;

and

forming, adjacent to the primary gate oxide layer, a primary gate for applying a bias voltage across the first capacitive dielectric.

6. The method of claim 1, further comprising forming the SOI substrate, including

doping a well in a silicon substrate;

and

forming over the doped well the buried oxide layer as a second capacitive dielectric.

7. The method of claim 6 wherein doping the well forms a back gate for applying a bias across the second capacitive dielectric.

8. A microcircuit, comprising:

a voltage supply;

an operational amplifier electrically coupled to the voltage supply, the operational amplifier having inverting and non-inverting input terminals and an output terminal; and

a capacitive field effect transistor coupled to the operational amplifier, the transistor including a doped substrate and a buried oxide layer within the doped substrate.

9. The microcircuit of claim 8 wherein the capacitive field effect transistor is a dual gate transistor including a primary gate and a secondary gate.

10. The microcircuit of claim 9 wherein the doped substrate functions as the secondary gate.

11. The microcircuit of claim 9 wherein the primary and secondary gates of the capacitive dual gate field effect transistor are coupled to different voltages to create different charge characteristics in a channel.

12. The microcircuit of claim 8, further comprising:

a current source coupled to the inverting input terminal;

a transistor coupled between the output terminal and the current source; and

a voltage divider coupled to the voltage supply and the non-inverting input terminal;

the microcircuit being operable as a reference voltage generator.

13. A microcircuit, comprising:

an input stage that receives an input signal at an input frequency;

an output stage that produces an output signal at an output frequency, the output signal coupled to the input stage; and

a filter stage coupled between the input stage and the output stage, the filter stage including a pair of capacitors in the form of dual gate transistors.

14. The microcircuit of claim 13 wherein the filter stage is operable as a loop filter.

15. The microcircuit of claim 13 wherein the filter stage further comprises a decoupling capacitor in the form of a dual gate transistor.

16. The microcircuit of claim 15 wherein the capacitors in the filter stage are PMOS dual gate transistors and the decoupling capacitor is an NMOS dual gate transistor.

17. The microcircuit of claim 15 wherein one or more of the dual gate transistors is a fully-depleted SOI dual gate transistor.

18. The microcircuit of claim 13 wherein

the input stage includes a phase frequency detector and a charge pump;

the output stage includes a PMOS field effect transistor and a current controlled oscillator; and

the microcircuit is operable as a charge pumped phase locked loop circuit.