CIRCUITS AND METHODS FOR REDUCING SUPPLY SENSITIVITY IN A POWER AMPLIFIER

• US 20160112018A1
• Filed: 10/20/2014
• Published: 04/21/2016
• Est. Priority Date: 10/20/2014
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Scuderi, Antonino, Hadjichristos, Aristotele
• Granted Patent: US 9,473,081 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H03F 1/223 with MOSFET's
• CPC Class Codes: H03F 1/56 Modifications of input or output impedances, not otherwise provided for
• CPC Class Codes: H03F 2200/18 the bias of the gate of a FET being controlled by a control signal
• CPC Class Codes: H03F 2200/222 A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier
• CPC Class Codes: H03F 2200/231 the input of an amplifier can be switched on or off by a switch to amplify or not an input signal
• CPC Class Codes: H03F 2200/234 the input amplifying stage being one or more operational amplifiers
• CPC Class Codes: H03F 2200/249 A switch coupled in the input circuit of an amplifier being controlled by a circuit, e.g. feedback circuitry being controlling the switch
• CPC Class Codes: H03F 2200/252 Multiple switches coupled in the input circuit of an amplifier are controlled by a circuit, e.g. feedback circuitry being controlling the switch
• CPC Class Codes: H03F 2200/321 Use of a microprocessor in an amplifier circuit or its control circuit
• CPC Class Codes: H03F 2200/366 Multiple MOSFETs are coupled in parallel
• CPC Class Codes: H03F 2200/387 A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
• CPC Class Codes: H03F 2200/411 the output amplifying stage of an amplifier comprising two power stages
• CPC Class Codes: H03F 2200/42 the input to the amplifier being made by capacitive coupling means
• CPC Class Codes: H03F 2200/432 Two or more amplifiers of different type are coupled in parallel at the input or output, e.g. a class D and a linear amplifier, a class B and a class A amplifier
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2200/522 the bias or supply voltage or current of the gate side of a FET amplifier being controlled to be on or off by a switch
• CPC Class Codes: H03F 2200/555 A voltage generating circuit being realised for biasing different circuit elements
• CPC Class Codes: H03F 2200/61 the cascode amplifier has more than one common gate stage
• CPC Class Codes: H03F 2200/75 the amplifier stage being a common source configuration MOSFET
• CPC Class Codes: H03F 2203/21106 An input signal being distributed in parallel over the inputs of a plurality of power amplifiers
• CPC Class Codes: H03F 2203/21136 : An input signal of a power amplifier being on/off switched
• CPC Class Codes: H03F 2203/21139 : An impedance adaptation circuit being added at the output of a power amplifier stage
• CPC Class Codes: H03F 2203/21142 : Output signals of a plurality of power amplifiers are parallel combined to a common output
• CPC Class Codes: H03F 2203/21178 : Power transistors are made by coupling a plurality of single transistors in parallel
• CPC Class Codes: H03F 2203/7215 : the gated amplifier being switched on or off by a switch at the input of the amplifier
• CPC Class Codes: H03F 2203/7236 : the gated amplifier being switched on or off by putting into parallel or not, by choosing between amplifiers by (a ) switch(es)
• CPC Class Codes: H03F 3/19 : with semiconductor devices only
• CPC Class Codes: H03F 3/193 : with field-effect devices H03F3/195 takes precedence
• CPC Class Codes: H03F 3/211 : using a combination of several amplifiers H03F3/60 takes precedence
• CPC Class Codes: H03F 3/245 : with semiconductor devices only
• CPC Class Codes: H03F 3/72 : Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
• CPC Class Codes: H03G 1/0029 : using FETs
• CPC Class Codes: H03G 1/0088 : using discontinuously variable devices, e.g. switch-operated
• CPC Class Codes: H03G 3/001 : Digital control of analog signals
• CPC Class Codes: H03G 3/007 : Control dependent on the supply voltage
• CPC Class Codes: H03G 3/3042 : in modulators, frequency-changers, transmitters or power amplifiers transmission power control in bidirectional transmission systems H04W52/04

Abstract

In one embodiment, the present disclosure includes a circuit comprising a first power amplifier stage having an input to receive an input signal, an output coupled to an output node, the first power amplifier stage receiving a time-varying power supply voltage. The circuit further includes a second power amplifier stage configured in parallel with the first power amplifier stage having an input to receive the input signal, an output coupled to the output node, the second power amplifier stage receiving the time-varying power supply voltage. A first gain of the first power amplifier stage decreases when the power supply voltage is in a first low voltage range, and a second gain of the second power amplifier stage compensates for the decreasing gain of the first power amplifier stage in the first low voltage range.

Claims

1. A circuit comprising:

a first power amplifier stage having an input to receive an input signal, an output coupled to an output node, the first power amplifier stage receiving a time-varying power supply voltage; and

a second power amplifier stage configured in parallel with the first power amplifier stage having an input to receive the input signal, an output coupled to the output node, the second power amplifier stage receiving the time-varying power supply voltage,

wherein a first gain of the first power amplifier stage decreases when the power supply voltage is in a first low voltage range, and wherein a second gain of the second power amplifier stage compensates for the decreasing gain of the first power amplifier stage in the first low voltage range.

2. The circuit of claim 1 wherein the first power amplifier stage comprises a first transistor, the first transistor having a control terminal coupled to receive the input signal and a first terminal coupled to the power supply voltage through the output node, and wherein the second power amplifier stage comprises a second transistor, the second transistor having a control terminal coupled to receive the input signal and a first terminal coupled to the power supply voltage through one or more stacked transistors and the output node.

3. The circuit of claim 2 wherein the first transistor is first device type and the second transistor is a second device type.

4. The circuit of claim 2 wherein the first transistor and the second transistor are coupled to different gate bias voltages.

5. The circuit of claim 2 wherein the first transistor and the second transistor are coupled to the same gate bias voltage.

6. The circuit of claim 2 wherein the one or more stacked transistors are two transistors configured in cascode.

7. The circuit of claim 2 wherein the second transistor comprises a plurality of segments, and wherein a different number of segments are activated based on the power supply voltage.

8. The circuit of claim 7 wherein the one or more of the segments comprise:

a source, a gate, and drain;

a first switch coupled between the gate and a reference voltage; and

a second switch coupled to the gate.

9. The circuit of claim 8 wherein the drains of the segments are coupled together, the sources of the segments are coupled together, and wherein when a segment is activated the first switch on a particular segment is opened and the second switch is closed to turn on the particular segment, and wherein when the segment is not activated the first switch is closed and the second switch is opened to turn off the particular segment.

10. The circuit of claim 1 wherein the first power amplifier stage comprises a first high voltage transistor, the first high voltage transistor having a control terminal coupled to receive the input signal and a first terminal coupled to the power supply voltage through the output node, and wherein the second power amplifier stage comprises a second standard transistor, the second standard transistor having a control terminal coupled to receive the input signal and a first terminal coupled to the power supply voltage through at least one high voltage transistor and the output node.

11. A method comprising:

receiving an input signal in a first power amplifier stage, and in accordance therewith, producing an output signal on an output node, the first power amplifier stage receiving a time-varying power supply voltage; and

receiving the input signal in a second power amplifier stage configured in parallel with the first power amplifier stage, and in accordance therewith, producing the output signal on the output node, the second power amplifier stage receiving the time-varying power supply voltage,

wherein a first gain of the first power amplifier stage decreases when the power supply voltage is in a first low voltage range, and wherein a second gain of the second power amplifier stage compensates for the decreasing gain of the first power amplifier stage in the first low voltage range.

12. The method of claim 11 wherein the first power amplifier stage comprises a first transistor, the method further comprising receiving the input signal on a control terminal of the first transistor, wherein a first terminal of the first transistor is coupled to the power supply voltage through the output node, and wherein the second power amplifier stage comprises a second transistor, the method further comprising receiving the input signal on a control terminal of the second transistor, wherein a first terminal of the second transistor is coupled to the power supply voltage through one or more stacked transistors and the output node.

13. The method of claim 12 wherein the first transistor is first device type and the second transistor is a second device type.

14. The method of claim 12 wherein the first transistor is high voltage MOS device, the one or more cascode transistors are high voltage MOS devices, and the second transistor is not a high voltage MOS device.

15. The method of claim 12 wherein the first transistor and the second transistor are coupled to different gate bias voltages.

16. The method of claim 12 wherein the first transistor and the second transistor are coupled to the same gate bias voltage.

17. The method of claim 12 wherein the second transistor comprises a plurality of segments, the method further comprising activating a different number of segments based on the power supply voltage.

18. The method of claim 17 wherein the one or more of the segments comprise:

a source, a gate, and drain;

a first switch coupled between the gate and a reference voltage; and

a second switch coupled to the gate.

19. The method of claim 18 wherein the drains of the segments are coupled together, the sources of the segments are coupled together, and wherein when a segment is activated the first switch on a particular segment is opened and the second switch is closed to turn on the particular segment, and wherein when the segment is not activated the first switch is closed and the second switch is opened to turn off the particular segment.

20. A circuit comprising:

first power amplifier means having an input to receive an input signal, an output coupled to an output node, the first power amplifier stage receiving a time-varying power supply voltage; and

second power amplifier means configured in parallel with the first power amplifier means having an input to receive the input signal, an output coupled to the output node, the second power amplifier stage receiving the time-varying power supply voltage,

wherein a first gain of the first power amplifier means decreases when the power supply voltage is in a first low voltage range, and wherein a second gain of the second power amplifier means compensates for the decreasing gain of the first power amplifier means in the first low voltage range.