Fractional-N Phase-Locked Loop

• US 20160112053A1
• Filed: 12/31/2015
• Published: 04/21/2016
• Est. Priority Date: 11/27/2013
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Perrott, Michael H.
• Granted Patent: US 9,461,653 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G04F 10/005 Time-to-digital converters [TDC] analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H03L 7/0802 the loop being adapted for reducing power consumption H03L7/14 takes precedence
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H03M 1/0836 of phase error, e.g. jitter
• CPC Class Codes: H03M 1/0854 of quantisation noise
• CPC Class Codes: H03M 1/66 Digital/analogue converters H03M1/001 – H03M1/10 take precedence
• CPC Class Codes: H03M 3/358 of non-linear distortion, e.g. instability avoiding instability by structural design H03M3/44
• CPC Class Codes: H03M 3/368 of noise other than the quantisation noise already being shaped inherently by delta-sigma modulators
• CPC Class Codes: H03M 7/3004 Digital delta-sigma modulation

Abstract

A phase-locked loop (PLL) includes a time to voltage converter to convert a phase error between a reference signal and a feedback signal of the PLL to one or more voltage signals. An oscillator-based analog to digital converter (ADC) receives the one or more voltage signals and controls one or more oscillators according to the voltages. The oscillator-based ADC determines a digital value corresponding to the phase error based on the frequencies of the one or more oscillators.

Claims

1. A phase-locked loop (PLL) comprising:

a capacitor based digital to analog converter (DAC) coupled to receive a digital indication of quantization noise and to supply a quantization noise correction voltage to adjust a phase error voltage to create a combined voltage signal with reduced quantization noise, wherein the phase error voltage is indicative of a phase error corresponding to a time difference between a reference signal and a feedback signal based on an output of a first oscillator, the first oscillator controlled at least in part based on a value of the combined voltage signal; and

an oscillator-based analog to digital converter (ADC) coupled the capacitor based DAC to convert the combined voltage signal to a digital value, the oscillator-based ADC having a second oscillator having a frequency responsive to the combined voltage signal.

2. The PLL as recited in claim 1 wherein the second oscillator is a ring oscillator and the oscillator-based ADC comprises:

first tuning transistors coupling stages of the ring oscillator to a first supply node and second tuning transistors coupling the stages of the ring oscillator to a second supply node.

3. The PLL as recited in claim 1 further comprising:

a phase detector circuit to supply a charge control signal corresponding to the phase error; and

a first capacitor circuit coupled to a first node to be charged by a current based on the charge control signal and supply the phase error voltage.

4. The PLL as recited in claim 3 further comprising:

a discharge switch coupled to the first node and controlled by a discharge signal to selectively discharge the first capacitor circuit according to the discharge signal.

5. The PLL as recited in claim 3 wherein the capacitive based DAC further comprises:

a storage circuit;

a plurality of capacitors coupled between the storage circuit storing respective digital bits for each of the capacitors and a second node.

6. The PLL as recited in claim 5 further comprising:

a first switch to selectively couple the second node to a first voltage according to a first control signal; and

a second switch to selectively couple the second node to a second according to a second control signal.

7. The PLL as recited in claim 6 wherein the storage circuit is coupled to be set or reset according to the first and second control signals.

8. The PLL as recited in claim 5 further comprising a binary to thermometer encoder coupled to supply a code corresponding to the quantization error.

9. The PLL as recited in claim 5 further comprising a coupling capacitor coupled between the first node and the second node, the coupling capacitor forming a part of the first capacitor circuit.

10. The PLL as recited in claim 1 further comprising a switch to couple the adjusted phase error voltage formed from the phase error signal and the quantization error correction voltage, to the oscillator-based ADC.

11. A method of operating a fractional-N phase-locked loop (PLL) comprising:

converting a phase error corresponding to a time difference between a reference signal and a feedback signal of the PLL to one or more voltage signals;

reducing quantization noise in the one or more voltage signals using one or more capacitor-based digital to analog converters (DACs) and generating one or more combined voltage signals with reduced quantization noise, the one or more combined voltage signals corresponding to a phase difference with reduced quantization noise;

controlling a frequency of an oscillator in an oscillator-based analog to digital converter (ADC) according to the one or more combined voltages; and

determining a digital value in the oscillator-based ADC corresponding to the phase difference with reduced quantization noise based on the frequency.

12. The method as recited in claim 11 further comprising:

generating a first voltage signal as one of the one or more combined voltage signals.

13. The method as recited in claim 12 further comprising:

supplying the first voltage signal to the oscillator of the oscillator-based ADC, the oscillator being a first ring oscillator; and

tuning a frequency of the first ring oscillator using the first voltage signal.

14. The method as recited in claim 13 further comprising:

counting transitions of the first ring oscillator to determine a first digital value corresponding to the phase difference with reduced quantization noise.

15. The method as recited in claim 12 further comprising:

generating a second voltage signal as one of the one or more combined voltage signals;

wherein the first voltage signal corresponds to a positive representation of the phase error with reduced quantization noise and the second voltage signal corresponds to a negative representation of the phase error with reduced quantization noise.

16. The method as recited in claim 15 further comprising:

supplying the first voltage signal to the first ring oscillator; and

supplying the second voltage signal to a second ring oscillator.

17. The method as recited in claim 15 further comprising supplying the second voltage signal to tune the first ring oscillator, a frequency of the first ring oscillator being based on the first and second voltage signals.

18. The method as recited in claim 17 further comprising:

supplying the first and second voltage signals to tune a second ring oscillator of the oscillator-based ADC; and

counting transitions of the second ring oscillator to determine a second digital value corresponding to the phase error with reduced quantization noise.

19. The method as recited in claim 18 further comprising combining the first digital value and the second digital value to generate the digital value of the oscillator-based ADC.