STOCHASTIC AND TOPOLOGICALLY AWARE ELECTROMIGRATION ANALYSIS METHODOLOGY

• US 20160116527A1
• Filed: 09/25/2015
• Published: 04/28/2016
• Est. Priority Date: 10/27/2014
• Status: Abandoned Application

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Jain, Palkesh
• Application Number:
  US14/865,339
• Publication Number:
  US 20160116527A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G01R 31/2848 using simulation
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

A computer-implemented method for analyzing a system comprising a plurality of components is described herein according to certain aspects. The method comprises simulating the system cascading through a plurality of failures until the system fails to meet a system specification, each of the failures corresponding to a failure of one of the components. The method also comprises estimating a time to failure of the system based on a last one of the plurality of failures.

Claims

1. A computer-implemented method for analyzing a system, the system comprising a plurality of components, the method comprising:

simulating the system cascading through a plurality of failures until the system fails to meet a system specification, each of the failures corresponding to a failure of one of the components; and

estimating a time to failure of the system based on a last one of the plurality of failures.

2. The method of claim 1, wherein each failure comprises an electromigration (EM) failure, an inter-layer dielectric breakdown, or a transistor failure.

3. The method of claim 1, wherein the components comprise a plurality of metal leads coupled in a grid.

4. The method of claim 3, wherein the grid comprises at least one of a power grid or a clock grid.

5. The method of claim 1, wherein the components comprise a plurality of buffers coupled in parallel.

6. The method of claim 5, wherein the plurality of buffers drive a clock grid.

7. The method of claim 1, wherein the system specification comprises a delay, or a skew.

8. The method of claim 1, further comprising:

for each of at least one of the failures, performing the steps of;

determining a change in current distribution in the system caused by the failure;

determining failure statistics for each of the components still functioning after the failure based on the change in the current distribution; and

determining a time to failure for a next one of the failures based on the determined failure statistics.

9. The method of claim 8, wherein determining the failure statistics for each of the components still functioning after the failure further comprises:

determining a cumulative probability distribution function (CDF) for the component based on current in the component after the failure; and

time shifting the CDF for the component based on a time of the failure.

10. The method of claim 8, wherein determining the change in the current distribution in the system caused by the failure further comprises treating the component corresponding to the failure as an open circuit.

11. An apparatus for analyzing a system, the system comprising a plurality of components, the apparatus comprising:

means for simulating the system cascading through a plurality of failures until the system fails to meet a system specification, each of the failures corresponding to a failure of one of the components; and

means for estimating a time to failure of the system based on a last one of the plurality of failures.

12. The apparatus of claim 11, wherein each failure comprises an electromigration (EM) failure, an inter-layer dielectric breakdown, or a transistor failure.

13. The apparatus of claim 11, wherein the components comprise a plurality of metal leads coupled in a grid.

14. The apparatus of claim 13, wherein the grid comprises at least one of a power grid or a clock grid.

15. The apparatus of claim 11, wherein the components comprise a plurality of buffers coupled in parallel.

16. The apparatus of claim 15, wherein the plurality of buffers drive a clock grid.

17. The apparatus of claim 11, wherein the system specification comprises a delay, or a skew.

18. The apparatus of claim 11, wherein, for each of at least one of the failures, the apparatus comprises:

means for determining a change in current distribution in the system caused by the failure;

means for determining failure statistics for each of the components still functioning after the failure based on the change in the current distribution; and

means for determining a time to failure for a next one of the failures based on the determined failure statistics.

19. The apparatus of claim 18, wherein the means for determining the failure statistics for each of the components still functioning after the failure further comprises:

means for determining a cumulative probability distribution function (CDF) for the component based on current in the component after the failure; and

means for time shifting the CDF for the component based on a time of the failure.

20. The apparatus of claim 18, wherein the means for determining the change in the current distribution in the system caused by the failure further comprises means for treating the component corresponding to the failure as an open circuit.

21. A computer-readable medium comprising instructions stored thereon that, when executed by a processor, cause the processor to:

simulate the system cascading through a plurality of failures until the system fails to meet a system specification, the system comprising a plurality of components, and each of the failures corresponding to a failure of one of the components; and

estimate a time to failure of the system based on a last one of the plurality of failures.

22. The computer-readable medium of claim 21, wherein each failure comprises an electromigration (EM) failure, an inter-layer dielectric breakdown, or a transistor failure.

23. The computer-readable medium of claim 21, wherein the components comprise a plurality of metal leads coupled in a grid.

24. The computer-readable medium of claim 23, wherein the grid comprises at least one of a power grid or a clock grid.

25. The computer-readable medium of claim 21, wherein the components comprise a plurality of buffers coupled in parallel.

26. The computer-readable medium of claim 25, wherein the plurality of buffers drive a clock grid.

27. The computer-readable medium of claim 21, wherein the system specification comprises a delay, or a skew.

28. The computer-readable medium of claim 21, wherein, for each of at least one of the failures, the computer-readable medium further comprises instructions for causing the processor to:

determine a change in current distribution in the system caused by the failure;

determine failure statistics for each of the components still functioning after the failure based on the change in the current distribution; and

determine a time to failure for a next one of the failures based on the determined failure statistics.

29. The computer-readable medium of claim 28, wherein the instructions for causing the processor to determine the failure statistics for each of the components still functioning after the failure further comprises instructions for causing the processor to:

determine a cumulative probability distribution function (CDF) for the component based on current in the component after the failure; and

time shift the CDF for the component based on a time of the failure.

30. The computer-readable medium of claim 28, wherein the instructions for causing the processor to determine the change in the current distribution in the system caused by the failure further comprises instructions for causing the processor to treat the component corresponding to the failure as an open circuit.