RESOURCE MAPPING IN MULTI-THREADED CENTRAL PROCESSOR UNITS

• US 20160117200A1
• Filed: 11/30/2015
• Published: 04/28/2016
• Est. Priority Date: 10/22/2014
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Alexander, Khary J., Helms, Markus, Jacobi, Christian, Nerz, Bernd, Urban, Volker
• Granted Patent: US 9,886,327 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 8/10 Requirements analysis; Specification techniques
• CPC Class Codes: G06F 8/314 Parallel programming languages G06F8/313 takes precedence
• CPC Class Codes: G06F 8/45 Exploiting coarse grain parallelism in compilation, i.e. parallelism between groups of instructions
• CPC Class Codes: G06F 9/5077 Logical partitioning of resources; Management or configuration of virtualized resources specific details on emulation or internal functioning of virtual machines G06F9/455
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Abstract

A processor determines that processing of a thread is suspended due to limited availability of a processing resource. The processor supports execution of the plurality of threads in parallel. The processor obtains a lock on a second processing resource that is substitutable as a resource during processing of the first thread. The second processing resource is included as part of a component that is external to the processor. The component supports a number of threads that is less than the plurality of threads. The processing of the thread is suspended until the lock is available. The processor processes the first thread using the second processing resource. The processor includes a shared register to support mapping a portion of the plurality of threads to the component. The portion of the plurality of threads is equal to, at most, the number of threads supported by component.

Claims

1. A method of a processor supporting multiple execution of threads in parallel, the method comprising:

determining, by a processor, that processing of a first thread of a plurality of threads is suspended due to limited availability of a first processing resource, wherein the processor supports execution of the plurality of threads in parallel;

obtaining, by the processor, a first lock on a second processing resource that is substitutable for the first processing resource during processing of the first thread, wherein the second processing resource is included as part of a component that is external to the processor, wherein the component supports a number of threads that is less than the plurality of threads, and wherein the processing of the first thread is suspended until the first lock is available; and

processing, by the processor, the first thread using the second processing resource, wherein the processor includes a shared register to support mapping of a portion of the plurality of threads to the component, and wherein that portion of the plurality of threads is equal to, at most, the number of threads that are supported by component.

2. The method of claim 1, the method further comprising:

determining, by the processor, that processing of a second thread of the plurality of threads is suspended to limited availability of the first processing resource;

determining, by the processor, whether the first lock on the second processing resource has been released; and

responsive to a determination that the first lock on the second processing resource has been released, obtaining, by the processor, a second lock on the second processing resource such that the second thread is processed using the second processing resource.

3. The method of claim 1, the method further comprising:

determining, by the processor, whether the first thread has been processed; and

responsive to a determination that the first thread has been processed, releasing, by the processor, the first lock on the second processing resource.

4. The method of claim 1, wherein the second processing resource is included as part of a component that operates in parallel with the processor.

5. The method of claim 4, wherein the second resource is statistically unlikely to be needed for the processing of more than the number of threads that are supported by the component.

6. The method of claim 1, wherein the second processing resource is a hardware resource.

7. The method of claim 1, wherein the component is a coprocessor that is configured to process one or more of:

mathematical calculations, input operations, output operations, and graphics operations.