DRIVE METHOD AND SYSTEM FOR LED DISPLAY PANEL
First Claim
1. A drive method for a LED display panel, wherein the method comprises:
- (a). Converting a HDMI/DVI video signal into an RGB signal by using a video signal decoder, and transmitting the RGB signal in parallel with a synchronous signal and a clock signal to a FPGA controller;
(b). Dividing the RGB signal into N independent code streams by using the FPGA controller, and after re-ranking, storing them in an external memory;
(c). Using N parallel LED drive modules to provide a direct current for the LED display panel, and periodically switching the direct current provided by N parallel LED drive modules at least between a first current I1 and a second current I2;
simultaneously using the N parallel LED drive modules correspondingly to receive the re-ranked N independent code streams, and adjusting the duty cycle of the direct current provided by the N parallel LED drive modules according to the re-ranked N independent code streams to keep the average current provided by the N parallel LED drive modules at a given current value IDC.
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Abstract
A drive method and system for an LED display panel. The method comprises: converting an HDMI/DVI video signal into an RGB signal; dividing the RGB signal into N independent code streams and re-ranking same; and periodically switching a direct current provided to an LED display module (30) at least between a first current I1 and a second current I2. The system comprises an FPGA controller (20), and a video signal decoder (10), a first external memory (41), a second external memory (42) and an LED display module (30) which are respectively connected to the FPGA controller (20). The FPGA controller (20) comprises N LED drive modules (231-23N) which are connected in parallel. The drive method and system can enhance the luminous efficacy of an LED, and can also conduct linear dimming on the LED.
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Citations
10 Claims
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1. A drive method for a LED display panel, wherein the method comprises:
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(a). Converting a HDMI/DVI video signal into an RGB signal by using a video signal decoder, and transmitting the RGB signal in parallel with a synchronous signal and a clock signal to a FPGA controller; (b). Dividing the RGB signal into N independent code streams by using the FPGA controller, and after re-ranking, storing them in an external memory; (c). Using N parallel LED drive modules to provide a direct current for the LED display panel, and periodically switching the direct current provided by N parallel LED drive modules at least between a first current I1 and a second current I2;
simultaneously using the N parallel LED drive modules correspondingly to receive the re-ranked N independent code streams, and adjusting the duty cycle of the direct current provided by the N parallel LED drive modules according to the re-ranked N independent code streams to keep the average current provided by the N parallel LED drive modules at a given current value IDC. - View Dependent Claims (2, 3, 4, 5)
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6. A drive system for a LED display panel, wherein the system comprises
a FPGA controller; -
a video signal decoder, a LED display module and at least two external memories, which are connected with the FPGA controller, respectively; and the FPGA controller comprises N parallel LED drive modules, wherein the video signal decoder for converting a HDMI/DVI video signal into an RGB signal, and then transmitting the RGB signal in parallel with a synchronous signal and a clock signal to the FPGA controller; the FPGA controller for dividing the RGB signal into N independent code streams, and after re-ranking, storing them in the external memories; the N parallel LED drive modules for receiving the re-ranked N independent code streams, and outputting at least a first current I1 and a second current I2 to the LED display module, wherein the N independent code streams used for adjusting the duty cycle of the current outputted by the N parallel LED drive modules to keep the average current outputted by the N parallel LED drive modules at a given current value IDC. - View Dependent Claims (7, 8, 9, 10)
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Specification