DRIVE METHOD AND SYSTEM FOR LED DISPLAY PANEL

• US 20160118026A1
• Filed: 03/27/2014
• Published: 04/28/2016
• Est. Priority Date: 04/01/2013
• Status: Active Grant

• Current Assignee: Hong Kong Polytechnic University
• Original Assignee: Hong Kong Polytechnic University
• Inventors: Loo, Ka Hong, Lai, Yuk Ming, Tse, Chi Kong Michael
• Granted Patent: US 10,043,493 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/0297 Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 2360/12 Frame memory handling
• CPC Class Codes: G09G 2360/18 Use of a frame buffer in a display terminal, inclusive of the display panel
• CPC Class Codes: G09G 2370/12 Use of DVI or HDMI protocol in interfaces along the display data pipeline
• CPC Class Codes: G09G 3/2014 by modulation of the duration of a single pulse during which the logic level remains constant
• CPC Class Codes: G09G 3/2096 Details of the interface to the display terminal specific for a flat panel suitable for both CRT and flat panel G09G5/006; specific for a CRT G09G1/167
• CPC Class Codes: G09G 3/32 semiconductive, e.g. using light-emitting diodes [LED]
• CPC Class Codes: G09G 3/3275 Details of drivers for data electrodes
• CPC Class Codes: G09G 3/3283 in which the data driver supplies a variable data current for setting the current through, or the voltage across, the light-emitting elements
• CPC Class Codes: G09G 5/399 using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers
• CPC Class Codes: H05B 45/20 Controlling the colour of the light
• CPC Class Codes: H05B 45/46 having LEDs disposed in parallel lines

Abstract

A drive method and system for an LED display panel. The method comprises: converting an HDMI/DVI video signal into an RGB signal; dividing the RGB signal into N independent code streams and re-ranking same; and periodically switching a direct current provided to an LED display module (30) at least between a first current I₁ and a second current I₂. The system comprises an FPGA controller (20), and a video signal decoder (10), a first external memory (41), a second external memory (42) and an LED display module (30) which are respectively connected to the FPGA controller (20). The FPGA controller (20) comprises N LED drive modules (231-23N) which are connected in parallel. The drive method and system can enhance the luminous efficacy of an LED, and can also conduct linear dimming on the LED.

Claims

1. A drive method for a LED display panel, wherein the method comprises:

(a). Converting a HDMI/DVI video signal into an RGB signal by using a video signal decoder, and transmitting the RGB signal in parallel with a synchronous signal and a clock signal to a FPGA controller;

(b). Dividing the RGB signal into N independent code streams by using the FPGA controller, and after re-ranking, storing them in an external memory;

(c). Using N parallel LED drive modules to provide a direct current for the LED display panel, and periodically switching the direct current provided by N parallel LED drive modules at least between a first current I₁ and a second current I₂;

simultaneously using the N parallel LED drive modules correspondingly to receive the re-ranked N independent code streams, and adjusting the duty cycle of the direct current provided by the N parallel LED drive modules according to the re-ranked N independent code streams to keep the average current provided by the N parallel LED drive modules at a given current value I_DC.

2. The drive method for a LED display panel of claim 1, wherein, in step S2, the FPGA controller stores the RGB signal into the external memory by using a ping-pong buffering method, and then divides the stored RGB signal into the N independent code streams.

3. The drive method for a LED display panel of claim 2, wherein, in step S2, the FPGA controller re-ranks the N independent code streams by using a bit-plane separation strategy in a digital video signal.

4. The drive method for a LED display panel of claim 1, wherein N is a natural number greater than or equal to 2, when N is equal to 2, the first current I₁ is greater than zero, and the peak value of the second current I₂ is twice that of the first current I₁, for generating the maximum illumination output set by the LED display module.

5. The drive method for a LED display panel of claim 1, wherein the current value I_DC is determined by the RGB signal and the maximum illumination output set by the LED display module.

6. A drive system for a LED display panel, wherein the system comprises

a FPGA controller;

a video signal decoder, a LED display module and at least two external memories, which are connected with the FPGA controller, respectively;

and the FPGA controller comprises N parallel LED drive modules, wherein

the video signal decoder for converting a HDMI/DVI video signal into an RGB signal, and then transmitting the RGB signal in parallel with a synchronous signal and a clock signal to the FPGA controller;

the FPGA controller for dividing the RGB signal into N independent code streams, and after re-ranking, storing them in the external memories;

the N parallel LED drive modules for receiving the re-ranked N independent code streams, and outputting at least a first current I₁ and a second current I₂ to the LED display module, wherein the N independent code streams used for adjusting the duty cycle of the current outputted by the N parallel LED drive modules to keep the average current outputted by the N parallel LED drive modules at a given current value I_DC.

7. The drive system for a LED display panel of claim 6, wherein the FPGA controller further comprises a data receiving module and a data partitioning module, wherein the data receiving module used for storing the RGB signal into the external memory with a ping-pong buffering method, and the data partitioning module used for dividing the stored RGB signal into the N independent code streams.

8. The drive system for a LED display panel of claim 7, wherein the FPGA controller further comprises a bit-plane separation module, wherein the bit-plane separation module used for re-ranking the N independent code streams by using a bit-plane separation strategy in a digital video signal.

9. The drive system for a LED display panel of claim 6, wherein N is a natural number greater than or equal to 2, when N is equal to 2, the first current I₁ is greater than zero, and the value of the second current I₂ is twice that of the first current for generating the maximum illumination output set by the LED display module.

10. The drive system for a LED display panel of claim 6, wherein the current value I_DC is determined by the RGB signal and the maximum illumination output set by the LED display module.