Adaptive Program Pulse Duration Based On Temperature

• US 20160118131A1
• Filed: 10/24/2014
• Published: 04/28/2016
• Est. Priority Date: 10/24/2014
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Dong, Yingda, Yuan, Jiahui, Chen, Jian
• Granted Patent: US 9,437,318 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects

Abstract

Techniques are provided for reducing program disturb in a memory device. The techniques include compensating for a temperature in the memory device to reduce the upshift in the threshold voltage (Vth) of erased-state memory cells. A minimum allowable program pulse duration increases with temperature to account for an increase in the attenuation of a program pulse along a word line. A program pulse duration which accounts for reduced channel boosting at relatively high temperatures is reduced as the temperature increases. An optimum program pulse duration is based on the larger of these durations. The optimum program pulse duration can also be based on factors such as a measure of program disturb or a memory hole width. Program disturb can also be reduced by easing the requirements of a verify test for the highest data state.

Claims

1. A method for operating a memory device, comprising:

obtaining data indicating a temperature of the memory device;

determining a program pulse duration which is at least as long as a minimum allowable program pulse duration, the minimum allowable program pulse duration is relatively long when the temperature is relatively high and compensates for a temperature-based change in a time constant of a selected word line in the memory device; and

programming a set of memory cells connected to the selected word line using program pulses having the program pulse duration.

2. The method of claim 1, wherein:

for temperatures below a breakpoint temperature, the program pulse duration increases with a decrease in the temperature; and

for temperatures above the breakpoint temperature, the program pulse duration increases with an increase in the temperature.

3. The method of claim 1, further comprising:

setting the program pulse duration to a larger of the minimum allowable program pulse duration and another pulse duration, the another pulse duration is relatively short when the temperature is relatively high and compensates for a temperature-based change in a channel boosting in the memory device.

4. The method of claim 1, wherein:

the selected word line is in a set of word lines;

each word line of the set of word lines is at a different height in the memory device and is adjacent to a portion of a vertical memory hole;

a width of the vertical memory hole varies along a height of the memory hole; and

the program pulse duration is based on a height of the selected word line in the memory device and is relatively short when a portion of the memory hole to which the selected word line is adjacent is relatively narrow.

5. The method of claim 1, wherein the set of memory cells comprises memory cells which are to be programmed to a highest target data state of a plurality of target data states by the programming, and the method further comprises:

adjusting a bit ignore number for the highest target data state based on the temperature, wherein the bit ignore number is relatively high when the temperature is relatively high, and the bit ignore number is a number of the memory cells which are to be programmed to the highest target data state which are permitted to fail a verify test of the highest target data state while still allowing the programming to be successfully completed.

6. The method of claim 5, wherein:

the set of memory cells comprises memory cells which are to be programmed to a target data state below the highest target data state; and

a bit ignore number for the memory cells which are to be programmed to the target data state below the highest target data state is not adjusted based on the temperature; and

the bit ignore number for the memory cells which are to be programmed to the target data state below the highest target data state is a number of the memory cells which are to be programmed to the target data state below the highest target data state which are permitted to fail a verify test of the target data state below the highest target data state while still allowing the programming to be successfully completed.

7. The method of claim 5, wherein:

the set of memory cells comprises memory cells which are to be programmed to a second highest target data state of the plurality of target data states; and

a bit ignore number for the memory cells which are to be programmed to the second highest target data state is adjusted based on the temperature by a smaller amount than an amount to which the bit ignore number is adjusted for the memory cells which are to be programmed to the highest target data state; and

the bit ignore number for the memory cells which are to be programmed to the second highest target data state is a number of the memory cells which are to be programmed to the second highest target data state which are permitted to fail a verify test of the second highest target data state while still allowing the programming to be successfully completed.

8. The method of claim 1, wherein the set of memory cells comprises memory cells which are to be programmed to a highest target data state of a plurality of target data states by the programming, and the method further comprises:

adjusting a verify voltage for the highest target data state based on the temperature, wherein the verify voltage is relatively low when the temperature is relatively high.

9. The method of claim 1, wherein:

the program pulses are provided on the word line by driving one end of the selected word line;

each program pulse has a peak amplitude at the one end of the selected word line; and

the minimum allowable program pulse duration is sufficiently long to ensure that the program pulses are within a specified range of the peak amplitude when the program pulses reach a memory cell of the set of memory cells which is furthest from the one end of the selected word line.

10. The method of claim 1, wherein:

the program pulses are provided on the selected word line by driving one end of the selected word line;

each program pulse has a peak amplitude for a time period at the one end of the selected word line; and

the minimum allowable program pulse duration is sufficiently long to ensure that the program pulses are within a specified range of the peak amplitude for at least a specified percentage of the time period when the program pulses reach a memory cell of the set of memory cells which is furthest from the one end of the selected word line.

11. The method of claim 1, further comprising:

determining a number of errors in programming a set of memory cells connected to another word line; and

setting the minimum allowable program pulse duration to be relatively long when the number of errors is relatively high.

12. The method of claim 1, further comprising:

determining a measure of program disturb in programming a set of memory cells connected to another word line; and

setting the minimum allowable program pulse duration to be relatively long when the measure of program disturb is relatively high, wherein the measure of program disturb is based on a measurement of an upper tail of a threshold voltage distribution of erased state memory cells in the set of memory cells connected to the another word line.

13. The method of claim 12, wherein:

the measurement of the upper tail is based on a number of memory cells in the set of memory cells connected to another word having a threshold voltage above a demarcation voltage.

14. A memory device, comprising:

a set of memory cells connected to a selected word line;

a driver at one end of the selected word line; and

a control circuit, the control circuit is configured to;

obtain data indicating a temperature of the memory device;

set a program pulse duration based on the temperature, wherein for temperatures below a breakpoint temperature, the program pulse duration increases with a decrease in the temperature and for temperatures above the breakpoint temperature, the program pulse duration increases with an increase in the temperature; and

program a set of memory cells connected to the selected word line using program pulses having the program pulse duration.

15. The memory device of claim 14, wherein the set of memory cells comprises memory cells which are to be programmed to a highest target data state of a plurality of target data states by the programming, and the method further comprises:

adjusting a bit ignore number for the highest target data state based on the temperature, wherein the bit ignore number is relatively high when the temperature is relatively high, and the bit ignore number is a number of the memory cells which are to be programmed to the highest target data state which are permitted to fail a verify test of the highest target data state while still allowing the programming to be successfully completed.

16. The memory device of claim 14, wherein:

the program pulses are provided on the word line by driving one end of the selected word line;

each program pulse has a peak amplitude at the one end of the selected word line; and

a minimum allowable program pulse duration is sufficiently long to ensure that the program pulses are within a specified range of the peak amplitude when the program pulses reach a memory cell of the set of memory cells which is furthest from the one end of the selected word line.

17. The memory device of claim 14, wherein:

the control circuit is configured to determine a measure of program disturb in programming a set of memory cells connected to another word line and set a minimum allowable program pulse duration to be relatively long when the measure of program disturb is relatively high; and

the measure of program disturb is based on a measurement of an upper tail of a threshold voltage distribution of erased state memory cells in the set of memory cells connected to the another word line.

18. A memory controller, comprising:

a storage device comprising a set of instructions, the set of instructions comprising;

instructions to obtain data indicating a temperature;

instructions to determine a minimum allowable program pulse duration based on the data, the minimum allowable program pulse duration is relatively long when the temperature is relatively high;

instructions to determine a program pulse duration which is at least as long as the minimum allowable program pulse duration; and

instructions to program a set of memory cells connected to a selected word line using program pulses having the program pulse duration; and

a processor operable to execute the set of instructions.

19. The memory controller of claim 18, wherein:

the minimum allowable program pulse duration compensates for a temperature-based change in a time constant of the selected word line in the memory device.

20. The memory controller of claim 18, wherein the set of instructions further comprises:

instructions to determine another pulse duration based on the data, the another pulse duration is relatively short when the temperature is relatively high; and

instructions to set the minimum allowable program pulse duration to a larger of the minimum allowable program pulse duration and the another pulse duration.