NONVOLATILE MEMORY DEVICE, OPERATING METHOD THEREOF AND MEMORY SYSTEM INCLUDING THE SAME

• US 20160118133A1
• Filed: 07/28/2015
• Published: 04/28/2016
• Est. Priority Date: 08/26/2010
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Original Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Inventors: NAM, SANG-WAN, YOON, CHI WEON, CHAE, DONGHYUK, PARK, JAE-WOO
• Granted Patent: US 9,947,416 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors

Abstract

A method of operating a non-volatile memory device includes performing an erasing operation to memory cells associated with a plurality of string selection lines (SSLs), the memory cells associated with the plurality of SSLs constituting a memory block, and verifying the erasing operation to second memory cells associated with a second SSL after verifying the erasing operation to first memory cells associated with a first SSL.

Claims

1. A method of erasing a nonvolatile memory device which includes a plurality of memory cell strings, the plurality of memory cell strings including first memory cell strings and second memory cell strings, the method comprising:

performing a first erasure operation to first memory cells included in the first memory cell strings connected to a first string selection line and second memory cells included in the second memory cell strings connected to a second string selection line, each of the first memory cell strings and the second memory cell strings including a plurality of nonvolatile memory cells connected in series and stacked in a direction substantially perpendicular to a substrate;

performing a first erasure verification operation to the first memory cells after the performing the first erasure operation to the first memory cells and the second memory cells; and

performing a second erasure verification operation to the second memory cells after the performing the first erasure verification operation to the first memory cells,

wherein at least one of the first memory cells and at least one of the second memory cells are connected to a word-line, and

one of the first memory cell strings and one of the second memory cell strings are connected to a bit-line.

2. The method of claim 1, further including performing a second erasure operation to the first memory cells and the second memory cells.

3. The method of claim 2, further including determining whether the second erasure verification operation is to be performed to the second memory cells, based on a first pass/fail result of the first erasure verification operation before the performing the second erasure operation.

4. The method of claim 3, further including, if the first pass/fail result is a fail, the second erasure verification operation is to be performed to the second memory cells after the performing the second erasure operation.

5. The method of claim 3, further including storing the first pass/fail result of the first erasure verification operation to the first memory cells,

wherein if the first pass/fail result is a pass, the second erasure verification operation is to be performed to the second memory cells before the performing the second erasure operation.

6. The method of claim 5, further including:

deleting the first pass/fail result after the performing the second erasure verification operation; and

storing a second pass/fail result of the second erasure verification operation.

7. The method of claim 1, further including performing a second erasure operation to the first memory cells and the second memory cells after the performing the second erasure verification operation to the second memory cells.

8. The method of claim 7, further including determining whether the first erasure verification operation is to be re-performed to the first memory cells after the performing the second erasure operation based on a first pass/fail result of the first erasure verification operation.

9. The method of claim 8, further including, if the first pass/fail result is a pass, the first erasure verification operation is not to be re-performed to the first memory cells after the performing the second erasure operation.

10. The method of claim 1, wherein the first memory cell strings and the second memory cell strings are connected to a ground selection line.

11. The method of claim 1, wherein each of the plurality of memory cell strings includes a first string selection transistor and a dummy cell.

12. The method of claim 11, wherein each of the plurality of memory cell strings includes a second string selection transistor connected to the first string selection transistor in series.

13. The method of claim 1, wherein the performing the first erasure operation further includes:

applying a first erase voltage to the substrate; and

floating a common source line connected to the plurality of memory cell strings.

14. A method of erasing a nonvolatile memory device which includes a plurality of memory cell strings, the plurality of memory cell strings including first memory cell strings and second memory cell strings, the method comprising:

performing a first erasure operation to first memory cells included in the first memory cell strings connected to a first string selection line and second memory cells included in the second memory cell strings connected to a second string selection line, each of the first memory cell strings and the second memory cell strings including a plurality of nonvolatile memory cells connected in series and stacked in a direction substantially perpendicular to a substrate;

performing a first erasure verification operation to the first memory cells after the performing the first erasure operation to the first memory cells and the second memory cells;

performing a second erasure verification operation to the second memory cells;

performing a second erasure operation to the first memory cells and the second memory cells; and

determining whether the second erasure verification operation is to be performed to the second memory cells before the performing the second erasure operation, based on a first pass/fail result of the first erasure verification operation,

wherein at least one of the first memory cells and at least one of the second memory cells are connected to a word-line, and

one of the first memory cell strings and one of the second memory cell strings are connected to a bit-line.

15. The method of claim 14, further including, if the first pass/fail result is a fail, the second erasure verification operation is not to be performed to the second memory cells before the performing the second erasure operation.

16. The method of claim 15, further including, if the first pass/fail result is a pass, the second erasure verification operation is to be performed to the second memory cells before the performing the second erasure operation.

17. The method of claim 16, wherein the performing the first erasure operation includes:

applying a first erase voltage to the substrate; and

floating a common source line connected to the plurality of memory cell strings.

18. A method of erasing a nonvolatile memory device which includes a plurality of memory cell strings, the plurality of memory cell strings including first memory cell strings and second memory cell strings, the method comprising:

performing a first operation, the first operation including;

performing a first erasure operation to first memory cells included in the first memory cell strings connected to a first string selection line and second memory cells included in the second memory cell strings connected to a second string selection line, each of the first memory cell strings and the second memory cell strings including a plurality of nonvolatile memory cells connected in series and stacked in a direction substantially perpendicular to a substrate;

performing a first erasure verification operation to the first memory cells after the performing the first erasure operation to the first memory cells and the second memory cells; and

performing a second erasure verification operation to the second memory cells after the performing the first erasure verification operation to the first memory cells; and

performing a second operation after the performing the first operation, the second operation including;

performing a second erasure operation to the first memory cells and the second memory cells;

determining whether re-performing the first erasure verification operation to the first memory cells based on a first pass/fail result of the first erasure verification operation of the first operation; and

determining whether re-performing the second erasure verification operation to the second memory cells based on a second pass/fail result of the second erasure verification operation of the first operation,

wherein at least one of the first memory cells and at least one of the second memory cells are connected to a word-line, and

one of the first memory cell strings and one of the second memory cell strings are connected to a bit-line.

19. The method of claim 18, wherein, if the first pass/fail result is a pass, the second operation is performed without re-performing the first erasure verification operation.

20. The method of claim 18, wherein, if the second pass/fail result is a fail, the second erasure verification operation of the second operation is re-performed.