NONVOLATILE MEMORY DEVICE, OPERATING METHOD THEREOF AND MEMORY SYSTEM INCLUDING THE SAME
First Claim
Patent Images
1. A method of erasing a nonvolatile memory device which includes a plurality of memory cell strings, the plurality of memory cell strings including first memory cell strings and second memory cell strings, the method comprising:
- performing a first erasure operation to first memory cells included in the first memory cell strings connected to a first string selection line and second memory cells included in the second memory cell strings connected to a second string selection line, each of the first memory cell strings and the second memory cell strings including a plurality of nonvolatile memory cells connected in series and stacked in a direction substantially perpendicular to a substrate;
performing a first erasure verification operation to the first memory cells after the performing the first erasure operation to the first memory cells and the second memory cells; and
performing a second erasure verification operation to the second memory cells after the performing the first erasure verification operation to the first memory cells,wherein at least one of the first memory cells and at least one of the second memory cells are connected to a word-line, andone of the first memory cell strings and one of the second memory cell strings are connected to a bit-line.
0 Assignments
0 Petitions
Accused Products
Abstract
A method of operating a non-volatile memory device includes performing an erasing operation to memory cells associated with a plurality of string selection lines (SSLs), the memory cells associated with the plurality of SSLs constituting a memory block, and verifying the erasing operation to second memory cells associated with a second SSL after verifying the erasing operation to first memory cells associated with a first SSL.
-
Citations
20 Claims
-
1. A method of erasing a nonvolatile memory device which includes a plurality of memory cell strings, the plurality of memory cell strings including first memory cell strings and second memory cell strings, the method comprising:
-
performing a first erasure operation to first memory cells included in the first memory cell strings connected to a first string selection line and second memory cells included in the second memory cell strings connected to a second string selection line, each of the first memory cell strings and the second memory cell strings including a plurality of nonvolatile memory cells connected in series and stacked in a direction substantially perpendicular to a substrate; performing a first erasure verification operation to the first memory cells after the performing the first erasure operation to the first memory cells and the second memory cells; and performing a second erasure verification operation to the second memory cells after the performing the first erasure verification operation to the first memory cells, wherein at least one of the first memory cells and at least one of the second memory cells are connected to a word-line, and one of the first memory cell strings and one of the second memory cell strings are connected to a bit-line. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
-
-
14. A method of erasing a nonvolatile memory device which includes a plurality of memory cell strings, the plurality of memory cell strings including first memory cell strings and second memory cell strings, the method comprising:
-
performing a first erasure operation to first memory cells included in the first memory cell strings connected to a first string selection line and second memory cells included in the second memory cell strings connected to a second string selection line, each of the first memory cell strings and the second memory cell strings including a plurality of nonvolatile memory cells connected in series and stacked in a direction substantially perpendicular to a substrate; performing a first erasure verification operation to the first memory cells after the performing the first erasure operation to the first memory cells and the second memory cells; performing a second erasure verification operation to the second memory cells; performing a second erasure operation to the first memory cells and the second memory cells; and determining whether the second erasure verification operation is to be performed to the second memory cells before the performing the second erasure operation, based on a first pass/fail result of the first erasure verification operation, wherein at least one of the first memory cells and at least one of the second memory cells are connected to a word-line, and one of the first memory cell strings and one of the second memory cell strings are connected to a bit-line. - View Dependent Claims (15, 16, 17)
-
-
18. A method of erasing a nonvolatile memory device which includes a plurality of memory cell strings, the plurality of memory cell strings including first memory cell strings and second memory cell strings, the method comprising:
-
performing a first operation, the first operation including; performing a first erasure operation to first memory cells included in the first memory cell strings connected to a first string selection line and second memory cells included in the second memory cell strings connected to a second string selection line, each of the first memory cell strings and the second memory cell strings including a plurality of nonvolatile memory cells connected in series and stacked in a direction substantially perpendicular to a substrate; performing a first erasure verification operation to the first memory cells after the performing the first erasure operation to the first memory cells and the second memory cells; and performing a second erasure verification operation to the second memory cells after the performing the first erasure verification operation to the first memory cells; and performing a second operation after the performing the first operation, the second operation including; performing a second erasure operation to the first memory cells and the second memory cells; determining whether re-performing the first erasure verification operation to the first memory cells based on a first pass/fail result of the first erasure verification operation of the first operation; and determining whether re-performing the second erasure verification operation to the second memory cells based on a second pass/fail result of the second erasure verification operation of the first operation, wherein at least one of the first memory cells and at least one of the second memory cells are connected to a word-line, and one of the first memory cell strings and one of the second memory cell strings are connected to a bit-line. - View Dependent Claims (19, 20)
-
Specification