Semiconductor Device and Method of Fabricating 3D Package With Short Cycle Time and High Yield

• US 20160118332A1
• Filed: 10/20/2015
• Published: 04/28/2016
• Est. Priority Date: 10/24/2014
• Status: Active Grant

• Current Assignee: Stats Chippac Limited
• Original Assignee: Stats Chippac Limited
• Inventors: Lin, Yaojian
• Granted Patent: US 9,653,445 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/214 Connecting portions
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/3511 : Warping
• CPC Class Codes: H01L 2924/3512 : Cracking
• CPC Class Codes: H01L 2924/35121 : Peeling or delaminating

Abstract

A method of making a semiconductor device comprises the steps of providing a first manufacturing line, providing a second manufacturing line, and forming a first redistribution interconnect structure using the first manufacturing line while simultaneously forming a second redistribution interconnect structure using the second manufacturing line. The method further includes the steps of testing a first unit of the first redistribution interconnect structure to determine a first known good unit (KGU), disposing a known good semiconductor die (KGD) over the first KGU of the first redistribution interconnect structure, testing a unit of the second redistribution interconnect structure to determine a second known good unit (KGU, and disposing the second KGU of the second redistribution interconnect structure over the first KGU of the first redistribution interconnect structure and the KGD. A resolution of the second manufacturing line is greater than a resolution of the first manufacturing line.

Claims

1. A method of making a semiconductor device, comprising:

providing a first manufacturing line;

providing a second manufacturing line;

forming a first redistribution interconnect structure using the first manufacturing line while simultaneously forming a second redistribution interconnect structure using the second manufacturing line;

testing a first unit of the first redistribution interconnect structure to determine a first known good unit (KGU);

disposing a known good semiconductor die (KGD) over the first KGU of the first redistribution interconnect structure;

testing a unit of the second redistribution interconnect structure to determine a second known good unit (KGU); and

disposing the second KGU of the second redistribution interconnect structure over the first KGU of the first redistribution interconnect structure and the KGD.

2. The method of claim 1, further including:

providing a third manufacturing line;

testing a semiconductor die of a semiconductor wafer to determine the KGD; and

dicing the KGD from the semiconductor wafer using the third manufacturing line while simultaneously forming the first redistribution interconnect structure using the first manufacturing line.

3. The method of claim 1, further including:

testing a second unit of the first redistribution interconnect structure to determine a rejected unit; and

disposing a dummy die over the rejected unit of the first redistribution interconnect structure.

4. The method of claim 1, wherein forming the second redistribution interconnect structure further includes disposing a discrete passive device over a conductive layer of the second redistribution interconnect structure.

5. The method of claim 1, wherein a resolution of the second manufacturing line is greater than a resolution of the first manufacturing line.

6. The method of claim 5, wherein forming the second redistribution interconnect structure includes using a resolution greater than the resolution of the first manufacturing line.

7. A method of making a semiconductor device, comprising:

providing a first manufacturing line;

providing a second manufacturing line;

forming a first redistribution interconnect structure using the first manufacturing line while simultaneously forming a second redistribution interconnect structure using the second manufacturing line;

testing a first unit of the first redistribution interconnect structure to determine a first known good unit (KGU); and

disposing a known good semiconductor die (KGD) over the first KGU of the first redistribution interconnect structure.

8. The method of claim 7, further including:

providing a third manufacturing line;

testing a semiconductor die of a semiconductor wafer to determine the KGD; and

dicing the KGD from the semiconductor wafer using the third manufacturing line while simultaneously forming the first redistribution interconnect structure using the first manufacturing line.

9. The method of claim 7, further including:

testing a second unit of the first redistribution interconnect structure to determine a rejected unit; and

disposing a dummy die over the rejected unit of the first redistribution interconnect structure.

10. The method of claim 7, wherein a resolution of the second manufacturing line is greater than a resolution of the first manufacturing line.

11. The method of claim 10, wherein forming the second redistribution interconnect structure includes using a resolution greater than the resolution of the first manufacturing line.

12. The method of claim 7, wherein forming the second redistribution interconnect structure further includes disposing a discrete passive device over a conductive layer of the second redistribution interconnect structure.

13. The method of claim 7, further including:

testing a unit of the second redistribution interconnect structure to determine a second known good unit (KGU); and

disposing the second KGU of the second redistribution interconnect structure over the first KGU of the first redistribution interconnect structure and the KGD.

14. A method of making a semiconductor device, comprising forming a first redistribution interconnect structure using a first manufacturing line while simultaneously forming a second redistribution interconnect structure using a second manufacturing line.

15. The method of claim 14, further including:

testing a first unit of the first redistribution interconnect structure to determine a first known good unit (KGU); and

disposing a known good semiconductor die (KGD) over the first KGU of the first redistribution interconnect structure.

16. The method of claim 15, further including:

testing a unit of the second redistribution interconnect structure to determine a second known good unit (KGU); and

disposing the second KGU of the second redistribution interconnect structure over the first KGU of the first redistribution interconnect structure and the KGD.

17. The method of claim 16, further including:

providing a third manufacturing line;

testing a semiconductor die of a semiconductor wafer to determine the KGD; and

dicing the KGD from the semiconductor wafer using the third manufacturing line while simultaneously forming the first redistribution interconnect structure using the first manufacturing line.

18. The method of claim 14, further including:

testing a second unit of the first redistribution interconnect structure to determine a rejected unit; and

disposing a dummy die over the rejected unit of the first redistribution interconnect structure.

19. The method of claim 14, wherein forming the second redistribution interconnect structure further includes disposing a discrete passive device over a conductive layer of the second redistribution interconnect structure.

20. The method of claim 14, wherein a resolution of the second manufacturing line is greater than a resolution of the first manufacturing line.

21. The method of claim 20, wherein forming the second redistribution interconnect structure includes using a resolution greater than the resolution of the first manufacturing line.

22. A semiconductor device, comprising:

a first redistribution interconnect structure including a known good unit (KGU) of the first redistribution interconnect structure and a rejected unit of the first redistribution interconnect structure;

a known good die (KGD) disposed over the KGU of the first redistribution interconnect structure; and

a dummy die disposed over the rejected unit of the first redistribution interconnect structure.

23. The semiconductor device of claim 22, further including a KGU of a second redistribution interconnect structure disposed over the KGD and KGU of the first redistribution interconnect structure.

24. The semiconductor device of claim 22, further including an encapsulant disposed over the KGU of the first redistribution interconnect structure, KGD, rejected unit of the first redistribution interconnect structure, and dummy die.

25. The semiconductor devices of claim 22, further including a discrete passive device disposed over the KGU of the first redistribution interconnect structure.