Semiconductor Device and Method of Fabricating 3D Package with Short Cycle Time and High Yield
First Claim
1. A method of making a semiconductor device, comprising:
- providing a first manufacturing line;
providing a second manufacturing line;
forming a first redistribution interconnect structure using the first manufacturing line while forming a second redistribution interconnect structure using the second manufacturing line;
testing a first unit of the first redistribution interconnect structure to determine a first known good unit (KGU);
disposing a known good semiconductor die (KGD) over the first KGU of the first redistribution interconnect structure;
dicing the first redistribution interconnect structure into KGUs;
testing a unit of the second redistribution interconnect structure to determine a second known good unit (KGU); and
disposing the first KGU of the first redistribution interconnect structure and the KGD over the second KGU of the second redistribution interconnect structure.
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Accused Products
Abstract
A method of making a semiconductor device comprising the steps of providing a first manufacturing line, providing a second manufacturing line, and forming a first redistribution interconnect structure using the first manufacturing line while forming a second redistribution interconnect structure using the second manufacturing line. The method further includes the steps of testing a first unit of the first redistribution interconnect structure to determine a first known good unit (KGU), disposing a known good semiconductor die (KGD) over the first KGU of the first redistribution interconnect structure, and dicing the first KGU and KGD from the first redistribution interconnect structure. The method further includes the steps of testing a unit of the second redistribution interconnect structure to determine a second KGU of the second redistribution interconnect structure and disposing first KGU of the first redistribution interconnect structure and the KGD over the second KGU of the second redistribution interconnect structure.
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Citations
25 Claims
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1. A method of making a semiconductor device, comprising:
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providing a first manufacturing line; providing a second manufacturing line; forming a first redistribution interconnect structure using the first manufacturing line while forming a second redistribution interconnect structure using the second manufacturing line; testing a first unit of the first redistribution interconnect structure to determine a first known good unit (KGU); disposing a known good semiconductor die (KGD) over the first KGU of the first redistribution interconnect structure; dicing the first redistribution interconnect structure into KGUs; testing a unit of the second redistribution interconnect structure to determine a second known good unit (KGU); and disposing the first KGU of the first redistribution interconnect structure and the KGD over the second KGU of the second redistribution interconnect structure. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method of making a semiconductor device, comprising:
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providing a first manufacturing line; providing a second manufacturing line; forming a first redistribution interconnect structure using the first manufacturing line while forming a second redistribution interconnect structure using the second manufacturing line; testing a first unit of the first redistribution interconnect structure to determine a first known good unit (KGU); disposing a known good semiconductor die (KGD) over the first KGU of the first redistribution interconnect structure; and dicing the first redistribution interconnect structure. - View Dependent Claims (8, 9, 10, 11, 12, 13)
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- 14. A method of making a semiconductor device, comprising forming a first redistribution interconnect structure and dicing the first redistribution interconnected structure into known good units using a first manufacturing line while forming a second redistribution interconnect structure using a second manufacturing line.
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22. A semiconductor device, comprising:
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a first redistribution interconnect structure including a known good unit (KGU) of the first redistribution interconnect structure and a rejected unit of the first redistribution interconnect structure, the KGU of the first redistribution structure including a known good die (KGD); and a second redistribution interconnect structure including a known good unit (KGU) of the second redistribution interconnect structure and a rejected unit of the second redistribution interconnect structure with the KGU of the first redistribution interconnect structure disposed over the KGU of the second redistribution interconnect structure and the rejected unit of the first redistribution interconnect structure disposed over the rejected unit of the second redistribution interconnect structure. - View Dependent Claims (23, 24, 25)
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Specification