Structure and Method for FinFET SRAM
First Claim
1. An integrated circuit (IC) layout, comprising:
- at least four first patterns located at a first layer of the IC layout, wherein the first patterns are spaced from each other in a first direction; and
each of the first patterns is an elongated shape extending lengthwise in a second direction that is orthogonal to the first direction;
at least four second patterns located at a second layer of the IC layout, wherein each of the second patterns is an elongated shape extending lengthwise in the second direction, the second patterns are spaced from each other in the first direction, each of the second patterns covers a side of one of the first patterns when the first and second layers are superimposed, the side extending in the second direction; and
third patterns located at a third layer of the IC layout, wherein the third patterns are spaced from each other, each of the third patterns covers a portion of another side of one of the first patterns that is not covered by the second patterns when the first, second, and third layers are superimposed, the another side extending in the second direction,wherein;
the first, second, and third patterns are used for collectively defining active regions for forming transistors; and
the active regions are defined along sides of the first patterns that extend in the second direction and are not covered by the second and third patterns when the first, second, and third layers are superimposed.
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Accused Products
Abstract
Provided is an embedded FinFET SRAM structure and methods of making the same. The embedded FinFET SRAM structure includes an array of SRAM cells. The SRAM cells have a first pitch in a first direction and a second pitch in a second direction orthogonal to the first direction. The first and second pitches are configured so as to align fin active lines and gate features of the SRAM cells with those of peripheral logic circuits. A layout of the SRAM structure includes three layers, wherein a first layer defines mandrel patterns for forming fins, a second layer defines a first cut pattern for removing dummy fins, and a third layer defines a second cut pattern for shortening fin ends. The three layers collectively define fin active lines of the SRAM structure.
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Citations
20 Claims
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1. An integrated circuit (IC) layout, comprising:
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at least four first patterns located at a first layer of the IC layout, wherein the first patterns are spaced from each other in a first direction; and
each of the first patterns is an elongated shape extending lengthwise in a second direction that is orthogonal to the first direction;at least four second patterns located at a second layer of the IC layout, wherein each of the second patterns is an elongated shape extending lengthwise in the second direction, the second patterns are spaced from each other in the first direction, each of the second patterns covers a side of one of the first patterns when the first and second layers are superimposed, the side extending in the second direction; and third patterns located at a third layer of the IC layout, wherein the third patterns are spaced from each other, each of the third patterns covers a portion of another side of one of the first patterns that is not covered by the second patterns when the first, second, and third layers are superimposed, the another side extending in the second direction, wherein; the first, second, and third patterns are used for collectively defining active regions for forming transistors; and the active regions are defined along sides of the first patterns that extend in the second direction and are not covered by the second and third patterns when the first, second, and third layers are superimposed. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A semiconductor device comprising:
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a first plurality of first SRAM cells, wherein the first plurality is arranged to have a first pitch in a first direction and a second pitch in a second direction orthogonal to the first direction, the first plurality includes FinFET transistors formed by first gate features and first fin active lines; a second plurality of peripheral logic circuits, wherein the second plurality includes FinFET transistors formed by second gate features and second fin active lines, the second gate features are arranged to have a third pitch in the second direction, and the second fin active lines are arranged to have a fourth pitch in the first direction; and a third plurality of second SRAM cells, wherein the third plurality is arranged to have a fifth pitch in the first direction and a sixth pitch in the second direction, the third plurality includes FinFET transistors formed by third gate features and third fin active lines, wherein; the second SRAM cells are different from the first SRAM cells; the second pitch is about twice of the third pitch; and the sixth pitch is about the same as the second pitch. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A mask set for semiconductor lithography process, comprising:
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a first mask having at least four first patterns, wherein the first patterns are spaced from each other in a first direction, and each of the first patterns is an elongated shape extending lengthwise in a second direction that is orthogonal to the first direction; a second mask having at least four second patterns, wherein each of the second patterns is an elongated shape extending lengthwise in the second direction, the second patterns are spaced from each other in the first direction, and each of the second patterns covers a side of one of the first patterns when the first and second masks are superimposed, the side extending in the second direction; and a third mask having third patterns, wherein the third patterns are spaced from each other, and each of the third patterns covers a portion of another side of one of the first patterns that is not covered by the second patterns when the first, second, and third masks are superimposed, the another side extending in the second direction, wherein; the first patterns define mandrels in a mandrel-spacer patterning process for forming spacers; and the second and third patterns define cut patterns for at least partially removing the spacers. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification