THREE-CHANNEL HIGH-SIDE GATE DRIVER HAVING STARTUP CIRCUIT AND CONFIGURABLE OUTPUTS

• US 20160118885A1
• Filed: 10/24/2014
• Published: 04/28/2016
• Est. Priority Date: 10/24/2014
• Status: Active Grant

• Current Assignee: TF Semiconductor Solutions, Inc. (Diodes Incorporated)
• Original Assignee: TF Semiconductor Solutions, Inc. (Diodes Incorporated)
• Inventors: Abdoulin, Edgar, Jeong, Jong Deog
• Granted Patent: US 9,374,006 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load
• CPC Class Codes: H02M 7/5387 in a bridge configuration
• CPC Class Codes: H03K 17/04123 in field-effect transistor switches
• CPC Class Codes: H03K 2217/0063 High side switches, i.e. the higher potential [DC] or life wire [AC] being directly connected to the switch and not via the load
• CPC Class Codes: H03K 2217/0081 Power supply means, e.g. to the switch driver

Abstract

A driver circuit includes three non-contiguous high-voltage wells formed within a low-voltage monolithic silicon substrate; a high-side driver circuit fabricated within each of the wells; a separate logic input path for each of the high-side driver circuits, each input path comprising a logic signal input terminal, a signal amplifier, a noise filter, a pulse generator, and a high-voltage level shifter; an output terminal for each driver circuit, each output terminal coupled to its associated driver circuit output through a separate mask-configurable, variable-value output resistor bank, which reduces the number of external components needed for driver circuitry; a startup circuit which prevents operation of an associated high-side switch during periods of line voltage instability; and embedded capacitor banks, each of which is in close proximity to a high-side switch, for reducing capacitive, resistive and inductance losses associated with long metal lines.

Claims

1. A driver circuit for switching a supply voltage across as few as one load and as many as three loads, said circuit comprising:

three non-contiguous high-voltage wells formed within a low-voltage monolithic silicon substrate;

a high-side driver fabricated within each of the three high-voltage wells, each high-side driver having

a half bridge consisting of a P-channel metal-oxide-semiconductor field-effect transistor (“

MOSFET”

) in series with an N-channel MOSFET, both MOSFETs sharing a common drain that serves as a driver output, said P-channel MOSFET having a source coupled to a floating supply input, and said N-channel MOSFET having a source coupled to a floating supply return,

a half-bridge control module having an output that is coupled to a gate of each MOSFET;

a separate logic input path for each of the high-side drivers, each input path comprising a logic signal input terminal, a signal amplifier, a noise filter, a pulse generator, and a high-voltage level shifter, in that order, wherein the signal amplifier, the noise filter, and the pulse generator of each path are positioned outside of the high-voltage well of their associated driver circuit, and the high-voltage level shifter, which has outputs that are coupled to the half-bridge control module, straddles the low-voltage substrate and the high-voltage well of its associated driver circuit; and

an output terminal for each high-side driver circuit, each output terminal coupled to its associated driver output through an output resistor bank having a resistance value that is set with a metal mask during manufacture.

2. The driver circuit of claim 1, wherein said resistor bank comprises a plurality of high-value resistors arranged in parallel, a desired resistance value of the bank being determined by a special fabrication mask which selects particular resistors in the bank to achieve the desired value.

3. The driver circuit of claim 1, which further comprises terminals for supply and return connections of a high-side floating supply voltage for each high-side driver.

4. The driver circuit of claim 3, wherein the high-side driver is packaged as a Small Outline Integrated Circuit (“

SOIC”

), with duplicate terminals being provided for at least some of the supply and return connections, thereby facilitating connections to power switches and sources from multiple sides of the SOIC, reducing parasitic elements that may adversely affect circuit performance in sensitive applications, as well as lowering operational noise and improving efficiency of the driver circuit.

5. The driver circuit of claim 1, which further comprises under-voltage detection and control circuitry located within each high-voltage well, said under-voltage detection and control circuitry preventing a driver output associated with that high-voltage well from turning on if a supply voltage is below a level required for efficient operation in turning on an external power switch that is controlled by the driver output.

6. The driver circuit of claim 5, wherein any deviations in the supply voltage from the required level which are less than a predetermined time interval are ignored, while deviations in the supply voltage from the required level which are greater than the predetermined time causes a disabling of the driver output until the deviations cease.

7. The driver circuit of claim 1, which further comprises an embedded capacitor bank in at least two of the high-voltage wells, each capacitor bank being in close proximity to one of three high-side switches that will be controlled by an output provided by one of said output terminals, thereby reducing capacitive, resistive, and inductive losses associated with long metal lines.

8. The driver circuit of claim 7, wherein said embedded capacitor banks also eliminate occurrences of false under-voltage lockouts.

9. The driver circuit of claim 1, wherein the noise filter in each input path eliminates occurrences of false turn-on and false turn-off of the high-side driver associated with that input path.

10. The driver circuit of claim 1, wherein noise filtering provided by the three noise filters is asymmetric so as more effectively eliminate false high-side turn on of each of the high-side drivers.

11. A driver circuit for controlling up to three high-side switches, each of which can apply a supply voltage across load, said circuit comprising:

three non-contiguous high-voltage wells formed within a low-voltage monolithic silicon substrate;

a high-side driver fabricated within each of the three high-voltage wells, each high-side driver having

a half bridge consisting of a P-channel metal-oxide-semiconductor field-effect transistor (“

MOSFET”

) in series with an N-channel MOSFET, both MOSFETs sharing a common drain that serves as a driver output to a gate of a high-voltage transistor switch, said P-channel MOSFET having a source coupled to a floating supply input, and said N-channel MOSFET having a source coupled to a floating supply return,

a half-bridge control module having an output that is coupled to a gate of each MOSFET;

a separate logic input path for each of the high-side drivers, each input path comprising a logic signal input terminal, a signal amplifier, a noise filter, a pulse generator, and a high-voltage level shifter, in that order, wherein the signal amplifier, the noise filter, and the pulse generator of each path are positioned outside of the high-voltage well of their associated driver circuit, and the high-voltage level shifter, which has outputs that are coupled to the half-bridge control module, straddles the low-voltage substrate and the high-voltage well of its associated driver circuit; and

an under-voltage detect module having an input coupled to the source of the P-channel MOSFET and an output coupled to the half-bridge control module, said under-voltage detect module preventing activation of the half-bridge control module whenever a voltage level at the floating supply input is inadequate for driving the high-side switches.

12. The driver circuit of claim 11, wherein any deviations in the supply voltage from the required level which are less than a predetermined time interval are ignored, while deviations in the supply voltage from the required level which are greater than the predetermined time causes a disabling of the driver output until the deviations cease.

13. The driver circuit of claim 11, which further comprises an embedded capacitor bank in at least two of the high-voltage wells, each capacitor bank being in close proximity to one of the three high-side switches that will be controlled by a single driver output, thereby reducing capacitive and resistance losses associated with long metal lines.

14. The driver circuit of claim 13, wherein said embedded capacitor banks also eliminate occurrences of false under-voltage lockouts.

15. The driver circuit of claim 11, wherein the noise filter in each input path is designed to eliminate false turn-on and false turn-off of the high-side driver associated with that input path.

16. The driver circuit of claim 11, wherein noise filtering provided by the three noise filters is asymmetric so as more effectively eliminate false high-side turn on of each of the high-side drivers.

17. The driver circuit of claim 11, which further comprises an output terminal for each high-side driver, each output terminal coupled to its associated driver output through an output resistor bank having a resistance value that is set with a metal mask during manufacture.

18. A driver circuit for controlling three high-side switches, each of which can apply a supply voltage to one of three windings of a three-phase brushless DC motor at predefined intervals, said circuit comprising:

three non-contiguous high-voltage wells formed within a low-voltage monolithic silicon substrate;

a high-side driver fabricated within each of the three high-voltage wells, each high-side driver having

a half bridge consisting of a P-channel metal-oxide-semiconductor field-effect transistor (“

MOSFET”

) in series with an N-channel MOSFET, both MOSFETs sharing a common drain that serves as a driver output to a gate of a high-voltage transistor switch, said P-channel MOSFET having a source coupled to a floating supply input, and said N-channel MOSFET having a source coupled to a floating supply return,

a half-bridge control module having an output that is coupled to a gate of each MOSFET;

a separate logic input path for each high-side driver circuit, each input path comprising a logic signal input terminal, a signal amplifier, a noise filter, a pulse generator, and a high-voltage level shifter, in that order, wherein the signal amplifier, the noise filter, and the pulse generator of each path are positioned outside of the high-voltage well of their associated driver circuit, and the high-voltage level shifter, which has outputs that are coupled to the half-bridge control module, straddles the low-voltage substrate and the high-voltage well of its associated driver circuit; and

an under-voltage detect module for each high-side driver circuit, said under-voltage detect module having an input coupled to the source of the P-channel MOSFET and an output coupled to the half-bridge control module, said under-voltage detect module preventing activation of the half-bridge control module whenever a voltage level at the floating supply input is inadequate for driving the high-side switches, each under-voltage detect module also incorporating timing components which create non-symmetric turn-on and turn-off threshold voltage values that reduce occurrences of false turn-ons and turn-offs of the associated high-side driver circuit.

19. The driver circuit of claim 18, which further comprises:

an output terminal for each high-side driver, each output terminal coupled to its associated driver output through an output resistor bank having a resistance value that is set with a metal mask during manufacture; and

an embedded capacitor bank in at least two of the high-voltage wells, each capacitor bank providing a reduction of capacitive and resistive losses associated with long metal lines that may be required to connect the output to of an associated high-side driver to a high-side switch.

20. The driver circuit of claim 18, where the filter for output turn-on is wider than the filter for output turn-off.