SOLID STATE IMAGING APPARATUS

• US 20160119565A1
• Filed: 05/28/2014
• Published: 04/28/2016
• Est. Priority Date: 06/07/2013
• Status: Active Grant

• Current Assignee: Hamamatsu Photonics KK
• Original Assignee: Hamamatsu Photonics KK
• Inventors: FUJITA, Kazuki, KYUSHIMA, Ryuji, MORI, Harumichi, SAWADA, Junichi
• Granted Patent: US 9,848,151 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14663 Indirect radiation imagers, e.g. using luminescent members
• CPC Class Codes: H04N 25/68 applied to defects
• CPC Class Codes: H04N 25/74 Circuitry for scanning or addressing the pixel array
• CPC Class Codes: H04N 25/767 Horizontal readout lines, multiplexers or registers
• CPC Class Codes: H04N 25/778 comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself

Abstract

A solid-state imaging device includes a photodetecting section, a vertical shift register section, first row selection lines, and second row selection lines. The vertical shift register section provides the row selection lines of the m-th row with common row selection signals.

Claims

1. A solid-state imaging device comprising:

a photodetecting section having M×

N pixels (each of M and N being an integer of 2 or more), each including one photodiode and first and second switch circuits each having one terminal connected to the one photodiode, two-dimensionally arrayed in M rows and N columns;

N readout lines provided for the respective columns and connected to the other terminals of the first and second switch circuits included in the pixels of the corresponding columns;

M first row selection lines provided for the respective rows and connected to control terminals of the first switch circuits included in the pixels of the corresponding rows;

M first buffers having respective output terminals connected to the M first row selection lines;

M second row selection lines provided for the respective rows and connected to control terminals of the second switch circuits included in the pixels of the corresponding rows;

M second buffers having respective output terminals connected to the M second row selection lines; and

a shift register section for generating a row selection signal for controlling an open/closed state of the first and second switch circuits for each row and providing input terminals of the first and second buffers with the common row selection signal, wherein

the shift register section has M signal output terminals provided one by one for the respective rows for outputting the row selection signal, the signal output terminals being connected to the input terminals of the first and second buffers of the corresponding rows.

2. The solid-state imaging device according to claim 1, wherein the first and second row selection lines are disposed in a region between the pixels.

3. The solid-state imaging device according to claim 1, wherein one row selection line of the first and second row selection lines is disposed in a region between the pixels, and the other row selection line is disposed on the pixel.

4. The solid-state imaging device according to claim 3, further comprising a reference potential line disposed between the other row selection line and the pixel.