MICROINTEGRATED ENCAPSULATED MEMS SENSOR WITH MECHANICAL DECOUPLING AND MANUFACTURING PROCESS THEREOF

• US 20160122181A1
• Filed: 08/27/2015
• Published: 05/05/2016
• Est. Priority Date: 10/31/2014
• Status: Active Grant

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Picco, Andrea
• Granted Patent: US 10,023,461 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: B81B 2201/0257 Microphones or microspeakers
• CPC Class Codes: B81B 2201/0264 Pressure sensors
• CPC Class Codes: B81B 7/0048 between the MEMS die and the substrate
• CPC Class Codes: B81B 7/0051 between the package lid and the substrate
• CPC Class Codes: B81B 7/0058 for protecting against damages due to external chemical or mechanical influences, e.g. shocks or vibrations
• CPC Class Codes: B81C 1/00325 for reducing stress inside of the package structure
• CPC Class Codes: B81C 2201/0116 Thermal treatment for structural rearrangement of substrate atoms, e.g. for making buried cavities
• CPC Class Codes: G01L 9/0042 Constructional details associated with semiconductive diaphragm sensors, e.g. etching, or constructional details of non-semiconductive diaphragms details about the integration or bonding of piezoresistor in or on the diaphragm G01L9/0052 and G01L9/0057 respectively
• CPC Class Codes: G01L 9/0054 integral with a semiconducting diaphragm

Abstract

The microintegrated sensor comprises a stack formed by a sensor layer, of semiconductor material, by a cap layer, of semiconductor material, and by an insulating layer. The sensor layer and the cap layer have a respective peripheral portion surrounding a central portion, and the insulating layer extends between the peripheral portions of the sensor layer and of the cap layer. An air gap extends between the central portions of the sensor layer and of the protection layer. A through trench extends into the central portion of the sensor layer as far as the air gap and surrounds a platform housing a sensitive element. The cap layer has through holes in the insulating layer that extend from the air gap and form a fluidic path with the air gap and the through trench.

Claims

1. A microintegrated sensor comprising:

a stack having a first surface and a second surface, the stack including;

a sensor layer at the first surface, the sensor layer including a peripheral portion surrounding a central portion, the central portion including a platform housing a sensitive element;

a cap layer at the second surface, the cap layer including a peripheral portion and a central portion, the central portion of the cap layer including a plurality of through holes;

an insulating layer located between the peripheral portions of the sensor layer and of the cap layer;

an air gap located between the central portions of the sensor layer and the cap layer; and

a plurality of through trenches in the central portion of the sensor layer, the plurality of through trenches, together, surrounding the platform housing the sensitive element, wherein the plurality of through holes, the air gap and the plurality of through trenches form a fluidic path to the sensitive element.

2. The sensor according to claim 1, comprising elastic connection regions in the sensor layer between the platform and the peripheral region of the sensor layer, the plurality of through trenches being defined by the elastic connection regions.

3. The sensor according to claim 1, wherein the sensor layer has a buried cavity and a membrane arranged between the buried cavity and the first surface, the membrane housing the sensitive element.

4. The sensor according to claim 3, comprising a protection region fixed to the peripheral portion of the cap layer and facing the membrane.

5. The sensor according to claim 4, wherein the protection region is an ASIC or an auxiliary cap.

6. The sensor according to claim 1, comprising an encapsulation region of resin surrounding the peripheral portions of the sensor layer, the cap layer, and the insulating layer.

7. The sensor according to claim 1, wherein the sensor is a piezoresistive pressure sensor.

8. The sensor according to claim 1, wherein plurality of through trenches completely surrounds the platform.

25. The sensor according to claim 1, wherein the stack is a SOI substrate.

9. A process comprising:

forming a stack that includes a sensor layer, a cap layer, and an insulating layer;

forming a plurality of through holes in a central portion of the cap layer;

forming a plurality of through trenches in a central portion in the sensor layer, the through trenches delimiting a platform in the sensor layer, the platform housing a sensitive element; and

forming an air gap between the central portions of the sensor layer and the cap layer, wherein the platform is in fluid communication with the plurality of holes in the cap layer through the air gap and the plurality of through trenches.

10. The process according to claim 9, wherein the stack is a SOI substrate.

11. The process according to claim 9, comprising forming, in the sensor layer, a buried cavity and a membrane facing the buried cavity, wherein the membrane is the sensitive element.

12. The process according to claim 11, further comprising fixing a protection region to a peripheral portion of the cap layer, the protection region facing the membrane.

13. The process according to claim 12, wherein the protection region is an ASIC or an auxiliary cap.

14. The process according to claim 9, wherein forming the plurality of through trenches comprises forming elastic connection regions extending into the sensor layer between the platform and a peripheral region of the sensor layer.

15. The process according to claim 9, wherein forming a plurality of through holes comprises removing selective portions of the cap layer and exposing the insulating layer, and forming the air gap comprises partially removing the insulating layer by etching a central portion of the insulating layer through the plurality of holes.

16. The process according to claim 9, further comprising forming an encapsulation region of resin around peripheral portions of the sensor layer, the cap layer, and the insulating layer.

17. The process according to claim 9, wherein forming the air gap between the central portion of the sensor layer and the cap layer comprises removing a central portion of the insulating layer through the plurality of through holes of the cap layer.

18. An electronic device comprising:

a microintegrated sensor including;

a semiconductor layer including a peripheral portion and a central portion, the central portion including a membrane configured to move in response to a change in pressure, the central portion including a plurality of through trenches that collectively substantially surrounds the membrane and mechanically decouples the membrane from the peripheral portion;

a cap layer coupled to the semiconductor layer and including a peripheral portion and a central portion, the cap layer including a plurality of through openings in the central portion of the cap layer;

an insulating layer between peripheral portions of the semiconductor layer and the cap layer, the insulating layer forming an air gap between the central portions of the membrane and the cap layer; and

a fluid path including the plurality of through openings in the central portion, the air gap, and the plurality of through trenches in the central portion of the semiconductor layer, wherein the fluid path places the membrane in fluid communication with an environment outside of the microintegrated sensor;

conductive bumps coupled to the microintegrated sensor;

an ASIC coupled to the microintegrated sensor by the conductive bumps;

encapsulation material surrounding side surfaces of the ASIC and the microintegrated sensor to form an electronic sensor package; and

a microprocessor coupled to the electronic sensor package.

19. The electronic device according to claim 18, wherein the plurality of through trenches forms springs in the semiconductor layer.

20. The electronic device according to claim 18, wherein the membrane faces the ASIC, and the membrane is spaced apart from the ASIC by the conductive bumps to form a gap.

21. The electronic device according to claim 18, wherein the membrane is suspended by a buried cavity formed in the semiconductor layer.

22. The electronic device according to claim 18, further comprising a memory coupled to the microprocessor and an input/output interface coupled to the microprocessor.

23. The electronic device according to claim 18, wherein the semiconductor layer is a first semiconductor layer, wherein the cap layer is a second semiconductor layer.

24. The electronic device according to claim 18, wherein collectively, the plurality of through trenches completely surrounds the membrane.

26. The electronic device according to claim 18, wherein the semiconductor layer, the insulating layer, and the cap layer collectively form a SOI substrate.