SEMICONDUCTOR TESTING FIXTURE AND FABRICATION METHOD THEREOF

• US 20160124019A1
• Filed: 10/30/2015
• Published: 05/05/2016
• Est. Priority Date: 10/30/2014
• Status: Active Grant

• Current Assignee: Tongfu Microelectronics Co., Ltd.
• Original Assignee: Nantong Fujitsu Microelectronics Company Limited
• Inventors: SHI, LEI
• Granted Patent: US 10,001,509 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G01R 1/06738 related to tip portion
• CPC Class Codes: G01R 1/06761 related to layers
• CPC Class Codes: G01R 1/07307 with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
• CPC Class Codes: G01R 3/00 Apparatus or processes specially adapted for the manufacture or maintenance of measuring instruments , e.g. of probe tips

Abstract

A semiconductor testing fixture is provided. The semiconductor testing fixture includes a substrate having a plurality of testing regions; and a plurality of testing probes with a predetermined distribution pattern formed on the substrate in each of the plurality of testing regions. Etch of the testing probes comprises a first testing tip; an insulation layer formed on a side surface of the first testing tip; and a second testing tip being coaxial with the first testing tip and surrounding the first testing tip formed on a side surface of the insulation layer.

Claims

1. A semiconductor testing fixture, comprising:

a substrate having a plurality of testing regions; and

a plurality of testing probes with a predetermined distribution pattern formed on the substrate in each of the plurality of testing regions,

wherein each of the plurality of testing probes comprises;

a first testing tip;

an insulation layer formed on a side surface of the first testing tip; and

a second testing tip being coaxial with the first testing tip and surrounding the first testing tip formed on a side surface of the insulation layer.

2. The semiconductor testing fixture according to claim 1, wherein:

the plurality of testing probes in each of the plurality of the testing regions are distributed as at least one row.

3. The semiconductor testing fixture according to claim 1, wherein:

the plurality of testing probes in each of the plurality of the testing regions are distributed as rows with a staggered arrangement.

4. The semiconductor testing fixture according to claim 1, wherein the first testing tip further comprises:

a first tip body with one end being configured as a first testing head and the other end being configured as a first connecting end.

5. The semiconductor testing structure according to claim 4, wherein the second testing tip further comprises:

a second tip body with one end being configured as a second testing head leveling with the first testing head of the first testing tip and the other end being configured as a second connecting end.

6. The semiconductor testing fixture according to claim 5, wherein the substrate further comprises:

a signal transmitting circuit including a first output terminal electrically connected with the first connecting end of the first testing tip, a second output terminal electrically connected with the second connecting end of the second testing tip, and a first input terminal and a second input terminal electrically connected with an external testing circuit.

7. The semiconductor testing fixture according to claim 5, wherein:

the first testing tip is a cylinder;

a diameter of the first testing tip is in a range of approximately 500 nm˜

500 μ

m;

a width of the insulation layer is in a range of approximately 80 nm˜

400 μ

m; and

a width of the second testing tip is in a range of approximately 60 nm˜

300 μ

m.

8. The semiconductor testing fixture according to claim 1, wherein:

the insulation layer is made of one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, and resin material.

9. The semiconductor testing fixture according to claim 1, further comprising:

a dielectric layer filling spaces between adjacent testing probes formed on the surface of the substrate.

10. The semiconductor testing fixture according to claim 9, further comprising:

a transition board having an insulation layer and a plurality of metal blocks in the insulation layer formed over the plurality of the testing probes.

11. A method for fabricating a semiconductor testing fixture, comprising:

providing a substrate having a plurality of testing regions; and

forming a plurality of testing probes with a predetermined distribution pattern on the substrate in each of the testing regions,

wherein each of the plurality of testing probes comprises;

a first testing tip;

an insulation layer formed on a side surface of the first testing tip; and

a second testing tip being coaxial with the first testing tip and surrounding the first testing tip formed on a side surface of the insulation layer.

12. The method according to claim 11, wherein:

the plurality of testing probes in each of the plurality of testing regions are distributed as at least one row.

13. The method according to claim 11, wherein:

the plurality of the first testing probes in each of the plurality of testing regions are distributed as rows having a staggered arrangement.

14. The method according to claim 11, wherein forming the plurality of testing probes in each of the plurality of testing regions further comprises:

forming a first metal layer on a surface of the substrate;

forming a plurality of first testing tips with the predetermined distribution pattern on the substrate in each of the plurality of testing regions by etching the first metal layer;

forming an insulation material layer covering top and side surfaces the plurality of first test tips on the surface of the substrate;

performing a mask-less etching process on the insulation layer to form an insulation layer on side surfaces of the first testing tips;

forming a second metal layer covering side surfaces of the insulation layer and the top surfaces of the first testing tips on the surface of the substrate; and

performing a mask-less etching process to form the second testing tips on the side surfaces of the insulation layer.

15. The method according to claim 14, after forming the plurality of testing probes in each of the plurality of testing regions, further comprising:

forming a dielectric layer filling spaces between adjacent testing probes on the surface of the substrate.

16. The method according to claim 11, wherein forming the plurality of testing probes in each of the plurality of testing regions further comprises:

forming a sacrificial layer having a plurality of openings with a predetermined distribution patterns and exposing the surface of the substrate on the substrate in each of the plurality of testing regions;

forming a first testing tip in etch of the plurality of openings by filling metal in the plurality of openings;

removing the sacrificial layer;

forming an insulation material layer covering top and side surfaces the first test tips on the surface of the substrate;

performing a mask-less etching process on the insulation layer to form an insulation layer on side surfaces of the first testing tips;

forming a second metal layer covering side surfaces of the insulation layer and the top surfaces of the first testing tips on the surface of the substrate; and

performing a mask-less etching process to form second testing tips on the side surfaces of the insulation layer.

17. The method according to claim 16, after forming the plurality of testing probes on the substrate in each of the plurality of testing regions, further comprising:

forming a dielectric layer filling spaces between adjacent testing probes on the surface of the substrate.

18. The method according to claim 11, wherein forming the plurality of testing probes on the substrate in each of the plurality of testing regions further comprises:

forming a dielectric layer on the surface of the substrate;

forming a plurality of first through-holes with the predetermined distribution pattern and a plurality of ring-shaped through-holes being coaxial with the first through-holes and surrounding the first through-holes in the dielectric layer in each of the plurality of testing region; and

forming a first testing tip in each of the plurality of first through-holes and a second testing tip in each of the plurality of ring-shaped through-holes.

19. The method according to claim 18, further comprising:

forming a transition board having an insulation layer and a plurality of metal blocks in the insulation layer with the metal blocks being connected with the plurality of testing probes over the dielectric layer.

20. The method according to claim 11, wherein:

the substrate includes a signal transmitting circuit configured to send testing signal to the plurality of the testing probes and receive electrical signals from the plurality of testing probes.