Edge Damage Inspection

• US 20160124039A1
• Filed: 10/26/2015
• Published: 05/05/2016
• Est. Priority Date: 10/30/2014
• Status: Active Grant

• Current Assignee: Bilban, Hermann, Eric Graetz, Rudolf Pairleitner
• Original Assignee: Infineon Technologies AG
• Inventors: Graetz, Eric, Bilban, Hermann, Pairleitner, Rudolf
• Granted Patent: US 9,658,279 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G01R 31/2607 Circuits therefor G01R31/2642 takes precedence
• CPC Class Codes: G01R 31/2656 using non-ionising electromagnetic radiation, e.g. optical radiation
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 29/0688 characterised by the particular shape of a junction between semiconductor regions
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A power semiconductor device includes a semiconductor body. The semiconductor body includes an active semiconductor region and a perimeter semiconductor region surrounding the active semiconductor region. The active semiconductor region has an active surface area, and the perimeter semiconductor region has a perimeter surface area. The power semiconductor device further includes a test structure for contactless testing of the perimeter semiconductor region. The test structure includes an electrically conductive path mounted on the perimeter surface area. The test structure is configured to extract energy from a remotely generated electromagnetic radio frequency test field.

Claims

1. A power semiconductor device, comprising:

a semiconductor body comprising an active semiconductor region and a perimeter semiconductor region surrounding the active semiconductor region, the active semiconductor region having an active surface area and the perimeter semiconductor region having a perimeter surface area; and

a test structure for contactless testing of the perimeter semiconductor region, the test structure comprising an electrically conductive path mounted on the perimeter surface area, wherein the test structure is configured to extract energy from a remotely generated electromagnetic radio frequency test field.

2. The power semiconductor device of claim 1, wherein the test structure is configured to produce a test signal based on the extracted energy, wherein the produced test signal is arranged to be detected by a test signal detector positioned remotely from the power semiconductor device.

3. The power semiconductor device of claim 1, wherein power semiconductor device further comprises an insulator electrically insulating the electrically conductive path from the perimeter semiconductor region and being at least partially included in the perimeter semiconductor region.

4. The power semiconductor device of claim 1, wherein the electrically conductive path completely surrounds the active surface area.

5. The power semiconductor device of claim 1, wherein the electrically conductive path contacts the perimeter semiconductor region.

6. The power semiconductor device of claim 1, wherein:

the test structure comprises a capacitor electrically coupled to the electrically conductive path; and

the test structure has at least one resonance frequency that is defined by an inductance of the electrically conductive path and a capacitance of the capacitor.

7. The power semiconductor device of claim 6, wherein the capacitor comprises a first electrode and a second electrode, the first electrode and the second electrode being mounted on the perimeter surface area, and wherein an electric field between the first electrode and the second electrode extends into the perimeter semiconductor region.

8. The power semiconductor device of claim 7, wherein the electrically conductive path, the first electrode and the second electrode form a monolithic component that is mounted on the perimeter surface area.

9. The power semiconductor device of claim 7, wherein the perimeter semiconductor region includes a well, the well comprising charge carriers of a first conductivity type, and wherein the electric field between the first electrode and the second electrode extends into the well.

10. The power semiconductor device of claim 9, wherein the well includes a first zone and a second zone, the first zone and the second zone each comprising charge carriers of a second conductivity type, and wherein the first zone contacts the first electrode and the second zone contacts the second electrode.

11. The power semiconductor device of claim 1, wherein the perimeter semiconductor region comprises at least one pn-junction, the at least one pn-junction being electrically coupled to the test structure.

12. The power semiconductor device of claim 1, wherein the test structure comprises a diode, the diode being electrically coupled to the electrically conductive path and configured to convert the extracted energy into a detectable light signal.

13. The power semiconductor device of claim 1, wherein the electrically conductive path comprises a first end and a second end spaced apart from each other, and wherein both the first end and the second end are electrically coupled to a bulk region of the power semiconductor device.

14. The power semiconductor device of claim 1, wherein the electrically conductive path is configured to convert the extracted energy into a detectable heat signal.

15. The power semiconductor device of claim 1, further comprising a first load contact structure mounted on the active surface area and electrically insulated from the test structure, wherein the first load contact structure is configured to feed a load current into the active semiconductor region.

16. The power semiconductor device of claim 1, wherein the electromagnetic radio frequency test field has a frequency that is at least twice as high as a frequency of an operating frequency range of the power semiconductor device.

17. The power semiconductor device of claim 1, wherein the semiconductor body comprises silicon carbide.

18. A method of manufacturing a power semiconductor device, the method comprising:

producing a semiconductor body that comprises an active semiconductor region and a perimeter semiconductor region surrounding the active semiconductor region, the active semiconductor region having an active surface area and the perimeter semiconductor region having a perimeter surface area;

on the active surface area, generating a front side metallization comprising a front side metallization material; and

on the perimeter surface area, producing a test structure for contactless testing of the perimeter semiconductor region, such that the test structure is configured to extract energy from a remotely generated electromagnetic radio frequency test field,

wherein producing the test structure includes generating an electrically conductive path on the perimeter surface area, the electrically conductive path comprising the same front side metallization material as the front side metallization.

19. The method of claim 18, wherein the front side metallization and the electrically conductive path are generated simultaneously.

20. The method of claim 18, wherein the front side metallization and the electrically conductive path are both generated by the same metallization apparatus.