Read Scrub with Adaptive Counter Management

• US 20160124679A1
• Filed: 10/29/2014
• Published: 05/05/2016
• Est. Priority Date: 10/29/2014
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Huang, Yichao, Avila, Chris, Lee, Dana, Chin, Henry, Dutta, Deepanshu, Raghu, Deepak, Puthenthermadam, Sarath
• Granted Patent: US 9,552,171 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0223 User address space allocation, e.g. contiguous or non contiguous base addressing
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 3/0608 Saving storage space on storage systems
• CPC Class Codes: G06F 3/0647 Migration mechanisms
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2211/5644 Multilevel memory comprising counting devices
• CPC Class Codes: G11C 2211/5648 Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant

Abstract

A number of complimentary techniques for the read scrub process using adaptive counter management are presented. In one set of techniques, in addition to maintaining a cumulative read counter for a block, a boundary word line counter can also be maintained to track the number of reads to most recently written word line or word lines of a partially written block. Another set of techniques used read count threshold values that vary with the number of program/erase cycles that a block has undergone. Further techniques involve setting the read count threshold for a closed (fully written) block based upon the number reads it experienced prior to being closed. These techniques can also be applied at a sub-block, zone level.

Claims

1. A method of operating a non-volatile memory circuit having a plurality of blocks formed according to a NAND type architecture in which memory cells of a block are formed along a plurality of word lines, and in which the word lines of a block are written in sequence from a first end to a second end thereof, the method comprising:

maintaining, for blocks in which one or more but less than all of the word lines have been written, first and second read counts, where the first read count tracks the cumulative number of reads for all word lines of the corresponding block, where the second read count tracks the cumulative number of reads to one or more of the last word lines in the write sequence of the corresponding block that is written at the time at which the read is performed, and wherein the first and second read counts are reset after an erase operation to the corresponding block; and

in response to either of the first or second read counts of a block reaching a respective first or second count threshold, marking the corresponding block for a data relocation operation.

2. The method of claim 1, wherein the second read count tracks the cumulative number of reads to the last word line in the write sequence of the corresponding block that is written at the time at which the read is performed.

3. The method of claim 2, further comprising:

maintaining for each of the blocks an experience count tracking the number program-erase cycles that the block has undergone, wherein one or both of the first and second count threshold values of a block vary with the block'"'"'s experience count.

4. The method of claim 2, further comprising:

subsequently rewriting the data content of the block marked for a data relocation operation to a different block.

5. The method of claim 2, wherein the non-volatile memory circuit is part of a memory system further including a controller circuit, wherein the first and second read counts are maintained by the controller.

6. The method of claim 2, wherein the memory cells of the non-volatile memory circuit are arranged in a two-dimensional array.

7. The method of claim 2, wherein the non-volatile memory circuit is a monolithic three-dimensional semiconductor memory device where the memory cells are arranged in multiple physical levels above a silicon substrate and comprise a charge storage medium.

8. The method of claim 2, further comprising:

resetting the second read counter in response to one or more word lines of the corresponding block being written.

9. The method of claim 1, wherein the second read count weights the contribution to the count from different ones of the one or more of the last word lines in the write sequence of the corresponding block that is written at the time at which the read is performed based upon proximity to the last of the last word line in the write sequence at the time at which the read is performed.

10. A method of operating a non-volatile memory circuit having a plurality of blocks in which memory cells of a block are formed along a plurality of word lines, the method comprising:

maintaining for each of the blocks an experience count tracking the number program-erase cycles that the block has undergone;

maintaining for each of the blocks a first read count tracking the cumulative number of reads for all word lines of the block since the block was last erased;

in response to incrementing one of the first read counts, performing a comparison of the incremented first read count to one of a plurality of first read count thresholds, wherein the first read count threshold used for the comparison is dependent upon the experience count of the corresponding block; and

in response to the incremented first read count reaching the used first read count threshold, marking the corresponding block for a data relocation operation.

11. The method of claim 10, wherein the first read count threshold is selected based upon which of a range of values the experience count belongs.

12. The method of claim 11, wherein the number of ranges of values is three.

13. The method of claim 11, wherein the first read count threshold used for the comparison is lower for higher experience counts.

14. The method of claim 10, wherein a correspondence between first read count thresholds and ranges of values the experience count is maintained as a look-up table.

15. The method of claim 10, wherein the blocks are formed according to a NAND type architecture in which memory cells of a block are formed along the block'"'"'s plurality of word lines, and in which the word lines of a block are written in sequence from a first end to a second end thereof, the method further comprising:

maintaining, for blocks in which one or more but less than all of the word lines have been written, a second read count that tracks the cumulative number of reads to the last word line in the write sequence of the corresponding block that is written at the time at which the read is performed, and wherein the second read count is reset after an erase operation to the corresponding block; and

in response to the second read count of a block reaching a respective second count threshold, marking the corresponding block for a data relocation operation.

16. The method of claim 10, further comprising:

subsequently rewriting the data content of the block marked for a data relocation operation to a different block.

17. The method of claim 10, wherein the non-volatile memory circuit is part of a memory system further including a controller circuit, wherein the first read counts and experience counts are maintained by the controller.

18. The method of claim 10, wherein the non-volatile memory circuit is formed according to a NAND type of architecture.

19. The method of claim 18, wherein the memory cells of the non-volatile memory circuit are arranged in a two-dimensional array.

20. The method of claim 18, wherein the non-volatile memory circuit is a monolithic three-dimensional semiconductor memory device where the memory cells are arranged in multiple physical levels above a silicon substrate and comprise a charge storage medium.

21. A method of operating a rewritable non-volatile memory circuit formed of a plurality of blocks each having multiple memory cells, comprising:

maintaining for partially written blocks a corresponding first read count, where the first read count tracks the cumulative number of reads of the corresponding block, and wherein the first read count is reset after an erase operation to the corresponding block; and

in response to a previously partially written block becoming fully written;

determining a corresponding closed block threshold for the block, wherein the corresponding closed block threshold is dependent upon the value of the corresponding first read count at the time at which the block becomes fully written;

resetting the corresponding first read count, where the first read count subsequently tracks the cumulative number of the number of reads to the corresponding block; and

in response to the first read count of the corresponding block reaching the corresponding closed block threshold, marking the block for a data relocation operation.

22. The method of claim 21, further comprising:

in response the first read count of a block reaching a first open block threshold prior to becoming fully written, marking the block for a data relocation operation and subsequently not writing to the block.

23. The method of claim 21, wherein determining the corresponding closed block threshold comprises:

if the first read count at the time at which the block becomes fully written is below a first value, using a first value for the closed block threshold; and

if the first read count at the time at which the block becomes fully written is above first value, using a reduced value for the closed block threshold.

24. The method of claim 23, wherein the reduced value is one of plurality of values corresponding the first value divided by a factor based on the first read count at the time at which the block becomes fully written.

25. The method of claim 21, wherein the blocks are formed according to a NAND type architecture in which memory cells of a block are formed along a plurality of word lines, and in which the word lines of a block are written in sequence from a first end to a second end thereof, the method further comprising:

maintaining for partially written blocks a second read count that tracks the cumulative number of reads to the last word line in the write sequence of the corresponding block that is written at the time at which the read is performed, and wherein the second read count is reset after an erase operation to the corresponding block; and

in response to the second read count of a block reaching a respective second count threshold, marking the corresponding block for a data relocation operation.

26. The method of claim 25, wherein the corresponding closed block threshold is further dependent upon the value of the corresponding second read count at the time at which the block becomes fully written.

27. The method of claim 21, further comprising:

subsequently rewriting the data content of the block marked for a data relocation operation to a different block.

28. The method of claim 21, wherein the non-volatile memory circuit is part of a memory system further including a controller circuit, wherein the first read counts are maintained by the controller.

29. The method of claim 21, wherein the non-volatile memory circuit is formed according to a NAND type of architecture.

30. The method of claim 29, wherein the memory cells of the non-volatile memory circuit are arranged in a two-dimensional array.

31. The method of claim 29, wherein the non-volatile memory circuit is a monolithic three-dimensional semiconductor memory device where the memory cells are arranged in multiple physical levels above a silicon substrate and comprise a charge storage medium.

32. A method of operating a non-volatile memory circuit having a plurality of blocks formed according to a NAND type architecture in which memory cells of a block are formed along a plurality of word lines, and in which the word lines of a block are written in sequence from a first end to a second end thereof, the method comprising:

maintaining a plurality of first read counts, where each of the first read count tracks the cumulative number of reads to a corresponding subset of word lines of the corresponding block, wherein each of the subsets is a plurality of adjacent word lines, and wherein the first read counts are reset after an erase operation to the corresponding block; and

in response to any of the first read counts of a block reaching a respective one of a plurality of first thresholds, marking the corresponding block for a data relocation operation.

33. The method of claim 32, wherein the plurality of first thresholds have the same value.

34. The method of claim 32, wherein at least one of the plurality of first thresholds has a value different from another of the first threshold values.

35. The method of claim 32, further comprising:

maintaining, for blocks in which one or more but less than all of the word lines have been written, a second read count, where the second read count tracks the cumulative number of reads to the last word line in the write sequence of the corresponding block that is written at the time at which the read is performed, and wherein the second read count is reset after an erase operation to the corresponding block; and

in response to the second read counts of a block reaching a respective second count threshold, marking the corresponding block for a data relocation operation.