Memory Bus Error Signal

• US 20160124797A1
• Filed: 06/27/2013
• Published: 05/05/2016
• Est. Priority Date: 06/27/2013
• Status: Abandoned Application

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Benedict, Melvin K.
• Application Number:
  US14/889,973
• Publication Number:
  US 20160124797A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/0751 Error or fault detection not based on redundancy power supply failures G06F1/30; network fault management H04L41/06
• CPC Class Codes: G06F 11/0772 Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers
• CPC Class Codes: G06F 11/079 Root cause analysis, i.e. error or fault diagnosis in a hardware test environment G06F11/22; in a software test environment G06F11/36
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: G06F 11/1405 at machine instruction level
• CPC Class Codes: G06F 11/141 for bus or memory accesses
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G11B 20/10222 clock-related aspects, e.g. phase or frequency adjustment or bit synchronisation dedicated sync patterns in the modulation code G11B20/1403

Abstract

A technique includes receiving, by a device a command, wherein a response to the command is expected from the device within a predetermined response time. The device may selectively generate an error signal to allow time for the device to complete processing the command.

Claims

1. A method comprising:

receiving, by a device, a command, wherein a corresponding response is expected within a predetermined response time; and

selectively generating, by the device, an error signal on a memory bus associated with the device to allow time for the device to complete processing the command, wherein the time for the device to complete processing the command is greater than the predetermined response time.

2. The method of claim 1, wherein selectively generating the error signal comprises generating a signal to cause a memory controller to replay at least one operation on the memory bus.

3. The method of claim 1, wherein selectively generating the error signal comprises accommodating a timing difference between a rate at which commands may be communicated over the memory bus and a timing at which the device processes the commands.

4. The method of claim 1, wherein selectively generating the error signal comprises generating a signal indicative of a parity error on the memory bus.

5. The method of claim 1, wherein selectively generating the error signal comprises generating the error to regulate a timing of commands communicated over a double data rate (DDR) memory bus.

6. The method of claim 1, wherein selectively generating the error signal comprises generating the error to regulate a time for a field programmable gate array (FPGA) to complete processing of a command.

7. The method of claim 1, further comprising communicating with volatile memory devices and the device over the memory bus.

8. A method comprising:

regulating a time for a device to complete processing of a command communicated to the device over a memory bus,

wherein the regulating comprises selectively generating an error signal to cause a memory controller to replay at least one operation on the memory bus.

9. The method of claim 8, wherein selectively generating the error signal comprises selectively generating a parity error signal.

10. The method of claim 8, wherein regulating the time comprises regulating a timing of commands communicated to the device over a double data rate (DDR) memory bus.

11. The method of claim 8, further comprising communicating with volatile devices over the memory bus.

12. The method of claim 8, wherein regulating the timing comprises accommodating a timing difference between a rate at which commands may be communicated over the memory bus and a timing at which the device processes the commands.

13. A system comprising:

a volatile memory device;

a device;

a memory bus to communicate commands to the volatile memory device and the device; and

a memory controller to initiate cycles on the memory bus to communicate the commands, wherein a timing specification of the bus controls a minimum time between the communication of successive commands via the memory bus and the timing specification is independent of time actually consumed by the device to process a given command communicated to the device via the memory bus,

wherein the device is adapted to selectively generate an error signal on the memory bus to delay completion of a bus operation associated with the given command to allow time for the device greater than the minimum time to process the given command.

14. The system of claim 13, wherein the error signal comprises a signal to cause the memory controller to replay at least one operation on the memory bus.

15. The system of claim 13, wherein the error signal indicates a parity error associated with at least one of a checksum of bit values corresponding to address lines of the memory bus and a checksum of bit values corresponding to data lines of the memory bus.