Memory Bus Error Signal
First Claim
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1. A method comprising:
- receiving, by a device, a command, wherein a corresponding response is expected within a predetermined response time; and
selectively generating, by the device, an error signal on a memory bus associated with the device to allow time for the device to complete processing the command, wherein the time for the device to complete processing the command is greater than the predetermined response time.
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Abstract
A technique includes receiving, by a device a command, wherein a response to the command is expected from the device within a predetermined response time. The device may selectively generate an error signal to allow time for the device to complete processing the command.
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Citations
15 Claims
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1. A method comprising:
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receiving, by a device, a command, wherein a corresponding response is expected within a predetermined response time; and selectively generating, by the device, an error signal on a memory bus associated with the device to allow time for the device to complete processing the command, wherein the time for the device to complete processing the command is greater than the predetermined response time. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method comprising:
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regulating a time for a device to complete processing of a command communicated to the device over a memory bus, wherein the regulating comprises selectively generating an error signal to cause a memory controller to replay at least one operation on the memory bus. - View Dependent Claims (9, 10, 11, 12)
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13. A system comprising:
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a volatile memory device; a device; a memory bus to communicate commands to the volatile memory device and the device; and a memory controller to initiate cycles on the memory bus to communicate the commands, wherein a timing specification of the bus controls a minimum time between the communication of successive commands via the memory bus and the timing specification is independent of time actually consumed by the device to process a given command communicated to the device via the memory bus, wherein the device is adapted to selectively generate an error signal on the memory bus to delay completion of a bus operation associated with the given command to allow time for the device greater than the minimum time to process the given command. - View Dependent Claims (14, 15)
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Specification