Data Storage Device and Flash Memory Control Method

• US 20160124820A1
• Filed: 08/28/2015
• Published: 05/05/2016
• Est. Priority Date: 11/03/2014
• Status: Active Grant

• Current Assignee: Silicon Motion Incorporated California (Silicon Motion)
• Original Assignee: Silicon Motion Incorporated California (Silicon Motion)
• Inventors: Lin, Wen-Sheng
• Granted Patent: US 9,870,321 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1435 using file system or storage system metadata
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7207 management of metadata or control data
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

A flash memory control technology with high reliability. In a power recovery process, a microcontroller is configured to duplicate a last write page of a run-time write block of a flash memory and thereby generate a duplicated page in the run-time write block. The microcontroller is further configured use the mapping information accessed from the duplicated page in rebuilding a physical-to-logical address mapping table rather than the mapping information accessed from the last write page. The microcontroller is configured to maintain the physical-to-logical address mapping table on a random access memory for the run-time write block and is further configured to use the physical-to-logical address mapping table to update a logical-to-physical address mapping table maintained in the flash memory.

Claims

1. A data storage device, comprising:

a flash memory, providing a storage space that is divided into a plurality of physical blocks with each physical block further divided into a plurality of physical pages; and

a control unit, comprising a microcontroller and a random access memory and coupled between a host and the flash memory,

wherein;

the microcontroller is configured to duplicate a last write page of a run-time write block between the plurality of physical blocks during a power recovery process and thereby generate a duplicated page in the run-time write block;

the microcontroller is configured to use mapping information accessed from the duplicated page in rebuilding a physical-to-logical address mapping table rather than mapping information accessed from the last write page;

the microcontroller is configured to maintain the physical-to-logical address mapping table on the random access memory for the run-time write block; and

the microcontroller is configured to update a logical-to-physical address mapping table in accordance with the physical-to-logical address mapping table, and the logical-to-physical address mapping table is maintained in the flash memory.

2. The data storage device as claimed in claim 1, wherein:

the microcontroller is configured to write dummy data into a next page with respect to the last write page during the power recovery process to make the next page with respect to the last write page a dummy page.

3. The data storage device as claimed in claim 2, wherein:

the duplicated page is in a next page with respect to the dummy page.

4. The data storage device as claimed in claim 3, wherein:

the microcontroller is configured to use mapping information accessed from physical page(s) prior to the last write page in rebuilding the physical-to-logical address mapping table before forming the dummy page.

5. The data storage device as claimed in claim 4, wherein:

the control unit further comprises an error checking and correction engine;

the microcontroller is configured to access the run-time write block page by page during the power recovery process and drive the error checking and correction engine to process each accessed page; and

the microcontroller is configured to not continue to use the spare space of the run-time write block when the error checking and correction engine fails to correct any page accessed from the run-time write block.

6. The data storage device as claimed in claim 5, wherein:

when determining that a specific page successfully processed by the error checking and correction engine during the power recovery process, the microcontroller is configured to use the mapping information accessed from a preceding page with respect to the specific page in rebuilding the physical-to-logical address mapping table; and

the specific page is the last write page or a physical page prior to the last write page in the run-time write block.

7. The data storage device as claimed in claim 1, wherein:

the microcontroller is configured to access the run-time write block page by page during the power recovery process until a blank page is accessed; and

the microcontroller is configured to regard a preceding page with respect to the blank page as the last write page.

8. A flash memory control method, comprising:

duplicating a last write page of a run-time write block between a plurality of physical blocks of a flash memory during a power recovery process and thereby generate a duplicated page in the run-time write block; and

using mapping information accessed from the duplicated page in rebuilding a physical-to-logical address mapping table rather than mapping information accessed from the last write page;

wherein the physical-to-logical address mapping table is maintained on the random access memory for the run-time write block and is used in updating a logical-to-physical address mapping table maintained in the flash memory.

9. The flash memory control method as claimed in claim 8, further comprising:

writing dummy data into a next page with respect to the last write page during the power recovery process to make the next page with respect to the last write page a dummy page.

10. The flash memory control method as claimed in claim 9, wherein:

the duplicated page is in a next page with respect to the dummy page.

11. The flash memory control method as claimed in claim 10, further comprising:

using mapping information accessed from physical page(s) prior to the last write page in rebuilding the physical-to-logical address mapping table before forming the dummy page.

12. The flash memory control method as claimed in claim 11, further comprising:

accessing the run-time write block page by page during the power recovery process and driving the error checking and correction engine to process each accessed page; and

not continuing to use the spare space of the run-time write block when the error checking and correction engine fails to correct any page accessed from the run-time write block.

13. The flash memory control method as claimed in claim 12, wherein:

when a specific page is determined successfully processed by the error checking and correction engine during the power recovery process, the mapping information accessed from a preceding page with respect to the specific page is used in rebuilding the physical-to-logical address mapping table; and

the specific page is the last write page or a physical page prior to the last write page in the run-time write block.

14. The flash memory control method as claimed in claim 8, further comprising:

accessing the run-time write block page by page during the power recovery process until a blank page is accessed; and

regarding a preceding page with respect to the blank page as the last write page.