SYSTEM INTERNAL LATENCY MEASUREMENTS IN REALTIME APPLICATIONS
First Claim
1. A method comprising:
- accessing a trigger signal from a plurality of trigger signals, the trigger signal including a pulse having a width;
detecting a rising edge of the pulse;
in response to the detecting of the rising edge, starting a counter;
detecting a falling edge of the pulse;
in response to the detecting of the falling edge;
stopping the counter;
comparing a count of the counter with first and second values stored in first and second registers, respectively, the first value representing a minimum pulse width and the second value representing a maximum pulse width;
storing the count in the first or second register based on a result of the comparing; and
dynamically adjusting a system clock frequency during runtime of an application based on the comparing.
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Accused Products
Abstract
Systems, methods, circuits and computer-readable mediums for system internal latency measurements in realtime applications are disclosed. In some implementations, a trigger signal is selected from a plurality of trigger signals for interrupting a processor of an integrated circuit system. The trigger signal includes a pulse having width. The system detects a rising edge of the pulse and starts a counter. The system detects a falling edge of the pulse and stops the counter. The system then compares a count of the counter with first and second values stored in first and second registers, respectively. The first value represents a minimum pulse width and the second value represents a maximum pulse width. The count is stored in the first or second register based on a result of the comparing.
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Citations
19 Claims
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1. A method comprising:
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accessing a trigger signal from a plurality of trigger signals, the trigger signal including a pulse having a width; detecting a rising edge of the pulse; in response to the detecting of the rising edge, starting a counter; detecting a falling edge of the pulse; in response to the detecting of the falling edge; stopping the counter; comparing a count of the counter with first and second values stored in first and second registers, respectively, the first value representing a minimum pulse width and the second value representing a maximum pulse width; storing the count in the first or second register based on a result of the comparing; and dynamically adjusting a system clock frequency during runtime of an application based on the comparing. - View Dependent Claims (2, 3, 4, 5)
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6. A system for performing system internal latency measurements, comprising:
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a selecting device configured to select a trigger signal from a plurality of trigger signals, the trigger signal including a pulse having width; a counter coupled to the selecting device and configured to;
start counting when a rising edge of the pulse is detected and stop counting when a falling edge of the pulse is detected;a compare and capture circuit coupled to the counter and configured to;
compare a count of the counter with first and second values stored in first and second registers, respectively, the first value representing a minimum pulse width and the second value representing a maximum pulse width; and
storing the count in the first or second register based on a result of the comparing. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13, 14)
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15. A non-transitory, computer-readable storage medium configured to store instructions, which, when executed by one or more processors, causes the one or more processors to perform operations comprising:
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accessing a trigger signal from a plurality of trigger signals, the trigger signal including a pulse having a width; detecting a rising edge of the pulse; in response to the detecting of the rising edge, starting a counter; detecting a falling edge of the pulse; in response to the detecting of the falling edge; stopping the counter; comparing a count of the counter with first and second values stored in first and second registers, respectively, the first value representing a minimum pulse width and the second value representing a maximum pulse width; storing the count in the first or second register based on a result of the comparing; and dynamically adjusting a system clock frequency during runtime of an application based on the comparing. - View Dependent Claims (16, 17, 18, 19)
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Specification