Method for operating a control device

• US 20160125202A1
• Filed: 10/15/2015
• Published: 05/05/2016
• Est. Priority Date: 10/30/2014
• Status: Abandoned Application

• Current Assignee: Robert Bosch GmbH
• Original Assignee: Robert Bosch GmbH
• Inventors: Pohl, Christopher, Hacioglu, Hamit, Stumpf, Frederic
• Application Number:
  US14/884,280
• Publication Number:
  US 20160125202A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 21/71 to assure secure computing or processing of information
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: G06F 9/4887 involving deadlines, e.g. rate based, periodic

Abstract

A method for operating a control device having a system-on-a-chip having a processor unit and a security processor unit, the processor unit and the security processor unit each having at least one processor core, the processor unit instructing the security processor unit to execute security-critical processes, a priority being assigned, by the processor unit or by the security processor unit, to each of the security-critical processes that are to be executed in the security processor unit, and the security-critical processes being executed in the security processor unit as a function of the respective priority.

Claims

1. A method for operating a control device having a system-on-a-chip having a processor unit and a security processor unit, the method comprising:

instructing, via the processor unit, the security processor unit to execute security-critical processes, the processor unit and the security processor unit each having at least one processor core;

assigning a priority, by the processor unit or by the security processor unit, to each of the security-critical processes that are to be executed in the security processor unit; and

executing the security-critical processes in the security processor unit as a function of the respective priority.

2. The method of claim 1, wherein:

if a first security-critical process having a first priority is executed in the security processor unit, and if the processor unit instructs the security processor unit to execute a second security-critical process having a second priority that is higher than the first priority,

the execution of the first security-critical process in the security processor unit is interrupted,

the second security-critical process is executed in the security processor unit, and

after execution of the second security-critical process, the execution of the first security-critical process in the security processor unit is continued.

3. The method of claim 2, wherein, when the execution of the first security-critical process in the security processor unit is interrupted, the current progress level of the execution is saved, and after execution of the second security-critical process the execution of the first security-critical process in the security processor unit is continued from this saved current progress level.

4. The method of claim 3, wherein the execution of the first security-critical process in the security processor unit is continued from this saved current progress level autonomously, without intervention of the processor unit.

5. The method of claim 1, wherein safety-critical processes that are to be executed in real time in the security processor unit are executed so that a real-time condition is met.

6. The method of claim 5, wherein the security-critical processes that are to be executed in real time are assigned a higher priority than security-critical processes that are not to be executed in real time.

7. The method of claim 1, wherein a real-time-capable operating system is executed in the security processor unit.

8. A computing unit for operating a control device having a system-on-a-chip having a processor unit and a security processor unit, comprising:

the processor unit to instruct the security processor unit to execute security-critical processes, the processor unit and the security processor unit each having at least one processor core; and

the processor unit or the security processor unit assigning a priority to each of the security-critical processes that are to be executed in the security processor unit;

wherein the security-critical processes are executed in the security processor unit as a function of the respective priority.

9. A computer readable medium having a computer program, which is executable by a processor, comprising:

a program code arrangement having program code for operating a control device having a system-on-a-chip having a processor unit and a security processor unit, by performing the following;

instructing, via the processor unit, the security processor unit to execute security-critical processes, the processor unit and the security processor unit each having at least one processor core;

assigning a priority, by the processor unit or by the security processor unit, to each of the security-critical processes that are to be executed in the security processor unit; and

executing the security-critical processes in the security processor unit as a function of the respective priority.

10. The computer readable medium of claim 9, wherein:

if a first security-critical process having a first priority is executed in the security processor unit, and if the processor unit instructs the security processor unit to execute a second security-critical process having a second priority that is higher than the first priority,

the execution of the first security-critical process in the security processor unit is interrupted,

the second security-critical process is executed in the security processor unit, and

after execution of the second security-critical process, the execution of the first security-critical process in the security processor unit is continued.