THREE DIMENSIONAL STACKED NONVOLATILE SEMICONDUCTOR MEMORY
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Accused Products
Abstract
A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks. The first block has a first cell unit which includes a memory cell to be programmed and a second cell unit which does not include a memory cell to be programmed, and programming is executed by applying a program potential or a transfer potential to word lines in the first block after the initial potential of channels of the memory cells in the first and second cell units is set to a plus potential. In the programming, the program potential and the transfer potential are not applied to word lines in the second block.
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Citations
15 Claims
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1. (canceled)
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2. :
- A controlling method for a memory including a first memory cell disposed in a first block and including a first gate and a first channel, a first transistor electrically connected to the first memory cell, a second memory cell disposed in the first block and including a second gate and a second channel, and a second transistor electrically connected to the second memory cell, the controlling method comprising;
boosting a voltage of the second channel to a first voltage when the first memory cell is selected by applying a second voltage to a gate of the first transistor and applying a third voltage to a gate of the second transistor in a write operation; and applying a program voltage to the first gate after said boosting. - View Dependent Claims (3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
- A controlling method for a memory including a first memory cell disposed in a first block and including a first gate and a first channel, a first transistor electrically connected to the first memory cell, a second memory cell disposed in the first block and including a second gate and a second channel, and a second transistor electrically connected to the second memory cell, the controlling method comprising;
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14. :
- A controlling method for a memory including a first memory string disposed in a first block and including a first memory cell and a first selection transistor, and a second memory string disposed in the first block and including a second memory cell and a second selection transistor, the controlling method comprising;
a first step of applying a first voltage to a gate of the second selection transistor and applying a second voltage to a gate of the first selection transistor, when the first memory cell is selected in a write operation; and applying a program voltage to a gate of the first memory cell after said first step. - View Dependent Claims (15)
- A controlling method for a memory including a first memory string disposed in a first block and including a first memory cell and a first selection transistor, and a second memory string disposed in the first block and including a second memory cell and a second selection transistor, the controlling method comprising;
Specification