METHOD FOR PRODUCING A PLURALITY OF MEASUREMENT REGIONS ON A CHIP, AND CHIP WITH MEASUREMENT REGIONS

• US 20160126151A1
• Filed: 05/30/2014
• Published: 05/05/2016
• Est. Priority Date: 05/30/2013
• Status: Active Grant

• Current Assignee: Boehringer Ingelheim Vetmedica GmbH (C.H. Boehringer Sohn AG & Co. KG)
• Original Assignee: Boehringer Ingelheim Vetmedica GmbH (C.H. Boehringer Sohn AG & Co. KG)
• Inventors: SCHIEBER, Markus, SCHOEDER, Heinz
• Granted Patent: US 9,735,072 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: B01J 2219/00317 Microwell devices, i.e. having large numbers of wells
• CPC Class Codes: B01J 2219/00619 using hydrophilic or hydrophobic regions
• CPC Class Codes: B01J 2219/00635 by reactive plasma treatment
• CPC Class Codes: B01J 2219/00637 by coating it with another layer
• CPC Class Codes: B01J 2219/00653 the compounds being bound to electrodes embedded in or on the solid supports
• CPC Class Codes: B01L 2200/12 Specific details about manufacturing devices
• CPC Class Codes: B01L 2300/0645 Electrodes
• CPC Class Codes: B01L 2300/0819 Microarrays; Biochips
• CPC Class Codes: B01L 2300/0861 Configuration of multiple channels and/or chambers in a single devices
• CPC Class Codes: B01L 2300/0887 Laminated structure
• CPC Class Codes: B01L 3/5088 confining liquids at a location by surface tension, e.g. virtual wells on plates, wires B01L3/50857 takes precedence
• CPC Class Codes: G01N 27/403 Cells and electrode assemblies
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes

Abstract

A a chip and a method for producing the chip with a plurality of measurement regions which are provided with electrodes for electrically detecting reactions in which, in order to reliably separate the individual measurement regions from one another, a monolayer of a fluorosilane is formed on the chip surface which has strongly hydrophobic properties. Therefore, during spotting with a liquid, the drops of liquid applied by spotting can be reliably prevented from coalescing, and thus, causing mixing of the substances in the drops of liquid which are supposed to be immobilized in the measurement regions.

Claims

1-38. -38. (canceled)

39. Method for producing a chip having a plurality of electrically addressable measurement regions or for producing a plurality of measurement regions on a chip, comprising:

structuring electrically contactable electrode pairings on the chip in each of the electrically addressable measurement regions, the measurement regions being formed by producing a compartmental structure which separates the measurement regions from one another, and

producing hydrophobic wetting properties on a chip surface outside of the measurement regions.

40. Method according to claim 39, wherein the formation of the compartmental structure comprises producing hydrophilic properties in the measurement regions.

41. Method according to claim 39, wherein the measurement regions are at least substantially provided with a protective layer or covered until the chips are divided or installed.

42. Method according to claim 41, wherein the protective layer is a photostructurable or photostructured layer.

43. Method according to claim 41, wherein the protective layer is thermally resistant at least to brief temperature peaks.

44. Method according to claim 41, wherein the protective layer is chemically and/or physically stable at least for brief periods at temperatures up to 150°

C.

45. Method according to claim 41, wherein the protective layer contains a photoresist or is a photoresist.

46. Method according to claim 45, wherein the photoresist is a polyamide-based photoresist.

47. Method according to claim 39, wherein the hydrophobic property is obtained by applying a hydrophobic lacquer coating or a monolayer.

48. Method according to claim 39, wherein the hydrophobic property is obtained by reactions with silanes.

49. Method according to claim 39, wherein the hydrophobic regions form a flat lattice between the measurement regions.

50. Method according to claim 39, wherein the formation of the compartmental structure is carried out using the following process steps:

producing hydrophobic wetting properties on the chip surface outside the measurement regions by applying a self-assembling monolayer formed of a fluorosilane compound, and

producing hydrophilic properties in the measurement regions.

51. Method according to claim 39, wherein the formation of the compartmental structure comprises the following process steps in the order specified:

vapor-depositing a fluorosilane compound as a monolayer on the chip surface,

applying a photostructurable layer to the chip surface,

illuminating the measurement regions,

developing the photostructurable layer, thereby exposing the measurement regions,

producing the hydrophilic properties in the measurement regions, and

removing the photostructured layer.

52. Method according to claim 39, wherein the formation of the compartmental structure comprises the following process steps in the order specified:

producing the hydrophilic properties on the chip surface,

applying a photostructurable layer to the chip surface,

illuminating the chip surface outside the measurement regions,

developing the photostructurable layer, the measurement regions being covered by the photostructured layer,

vapor-depositing a fluorosilane compound as a monolayer on the chip surface, and

removing the photostructured layer.

53. Method according to claim 39, wherein the production of the hydrophilic properties is carried out in an oxygen plasma or by dry etching.

54. Method according to claim 39, wherein after the completion of the processed chip surface, at least the measurement regions are cleaned.

55. Method according to claim 54, wherein the cleaning is carried out by a wet chemical method using a piranha solution.

56. Method according to claim 54, wherein after the cleaning has been completed, functionalization of the measurement regions is carried out with a spotting process.

57. Method according to claim 39, wherein the hydrophobic intermediate regions have a width between the measurement regions of more than 10% that of a measurement region.

58. Chip having a plurality of electrically addressable measurement regions, wherein a compartmental structure separates the measurement regions from one another on the chip surface, wherein the compartmental structure has at least one of a hydrophobic layer and a self-assembling monolayer.

59. Chip according to claim 58, wherein the chip surface is at least substantially planar and the compartmental structure is raised relative thereto.

60. Chip according to claim 58, wherein electrically contactable electrode pairings are structured in each of the measurement regions on the chip.

61. Chip according to claim 58, wherein the compartmental structure surrounds each measurement region completely or annularly with a hydrophobic layer or a hydrophobic intermediate region.

62. Chip according to claim 58, wherein the compartmental structure or hydrophobic layer or monolayer is of lattice-shaped and/or honeycomb-shaped configuration.

63. Chip according to claim 58, wherein the hydrophobic layer is configured as a flat coating.

64. Chip according to claim 58, wherein the compartmental structure or hydrophobic layer is smaller in height than in width and the width between two adjacent measurement regions is greater than the height relative to the chip surface carrying the measurement regions by at least a factor 5.

65. Chip according to claim 58, wherein the height of the compartmental structure is less than 2 μ

m and more than 10 nm.

66. Chip according to claim 58, wherein the compartmental structure or hydrophobic layer or monolayer forms hydrophobic intermediate regions between the measurement regions.

67. Chip according to claim 66, wherein the intermediate regions between the measurement regions have a width between the measurement regions of more than 20%, of a measurement region.

68. Chip according to claim 66, wherein the intermediate regions have a width between the measurement regions of more than 5 μ

m.

69. Chip according to claim 58, wherein the compartmental structure or the hydrophobic layer or monolayer has a contact angle with water of substantially at least 90°

.

70. Chip according to claim 58, wherein the compartmental structure is formed from the self-assembling monolayer of a fluorosilane compound which covers the chip surface outside the measurement regions.

71. Chip according to claim 58, wherein the hydrophobic layer contains a fluorosilane compound or is formed therefrom.

72. Chip according to claim 58, wherein the monolayer is of a hydrophobic nature.

73. Chip according to claim 58, wherein the hydrophobic layer contains a photoresist or is a photoresist.

74. Chip according to claim 73, wherein the photoresist is a polyamide-based photoresist.

75. Chip according to claim 58, wherein the compartmental structure or hydrophobic layer or monolayer is at least briefly chemically and physically stable at temperatures up to 150°

C.

76. Chip having a plurality of electrically addressable measurement regions, wherein a compartmental structure separates the measurement regions from one another on the chip surface, wherein the compartmental structure has a hydrophobic layer, wherein the hydrophobic layer contains a photoresist or is a photoresist and wherein the chip surface is at least substantially planar and the compartmental structure is raised relative thereto.

77. Chip according to claim 76, wherein the photoresist is a polyamide-based photoresist.

78. Chip according to claim 76, wherein electrically contactable electrode pairings are structured in each of the measurement regions on the chip.

79. Chip according to claim 76, wherein the compartmental structure surrounds each measurement region completely or annularly with a hydrophobic layer or a hydrophobic intermediate region.

80. Chip according to claim 76, wherein the compartmental structure or hydrophobic layer is of lattice-shaped and/or honeycomb-shaped configuration.

81. Chip according to claim 76, wherein the compartmental structure or hydrophobic layer is smaller in height than in width and the width between two adjacent measurement regions is greater than the height relative to the chip surface carrying the measurement regions by at least a factor 5.

82. Chip according to claim 76, wherein the compartmental structure or hydrophobic layer forms hydrophobic intermediate regions between the measurement regions.

83. Chip according to claim 82, wherein the intermediate regions between the measurement regions have a width between the measurement regions of more than 20%, of a measurement region.

84. Chip according to claim 82, wherein the intermediate regions have a width between the measurement regions of more than 5 μ

m.

85. Chip according to claim 76, wherein the compartmental structure or the hydrophobic layer has a contact angle with water of substantially at least 90°

.

86. Chip according to claim 76, wherein the compartmental structure or hydrophobic layer is at least briefly chemically and physically stable at temperatures up to 150°

C.