ARRAY SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE

• US 20160126257A1
• Filed: 05/27/2015
• Published: 05/05/2016
• Est. Priority Date: 10/29/2014
• Status: Active Grant

• Current Assignee: Shanghai Tianma Micro-Electronics Company Limited (Tianma Microelectronics Company Limited), Tianma Microelectronics Company Limited
• Original Assignee: Shanghai Tianma Micro-Electronics Company Limited (Tianma Microelectronics Company Limited), Tianma Microelectronics Company Limited
• Inventors: CAO, Zhaokeng, Qin, Dandan, Cui, Tingting, Xi, Kerui
• Granted Patent: US 9,455,277 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G02F 1/13306 Circuit arrangements or driving methods for the control of single liquid crystal cells G02F1/132, G02F1/133382 take precedence
• CPC Class Codes: G02F 1/133382 Heating or cooling of liquid crystal cells other than for activation, e.g. circuits or arrangements for temperature control, stabilisation or uniform distribution over the cell
• CPC Class Codes: G02F 1/133514 Colour filters
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2201/40 Arrangements for improving the aperture ratio
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2300/043 Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
• CPC Class Codes: G09G 2320/041 Temperature compensation
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: H01L 27/1218 with a particular composition or structure of the substrate
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors

Abstract

An array substrate includes a substrate, a plurality of gate lines and a plurality of data lines intersecting each other and being insulating from each other, and a plurality of pixel units arranged in an array and surrounded by the intersecting gate lines and data lines. The array substrate also includes at least one temperature measuring unit and at least one gate signal start control line. The temperature measuring unit includes at least one thin film transistor. The array substrate further includes a signal input line, a signal output line, and resistor is arranged on the signal input line. The temperature measuring unit includes a first terminal electrically connected with the signal input line and a second terminal electrically connected with the signal output line.

Claims

1. An array substrate comprising:

a substrate;

a plurality of gate lines and a plurality of data lines arranged on the substrate, the gate lines intersecting the data lines and being insulated from the data lines;

a plurality of pixel units arranged in an array and surrounded by the intersecting gate lines and the data lines;

a gate signal start control line;

a signal input line and a signal output line;

a resistor connected in series to the signal input line; and

a temperature measuring unit comprising at least one thin film transistor, a first terminal electrically connected with the signal input line, and a second terminal electrically connected with the signal output line.

2. The array substrate of claim 1, wherein the temperature measuring unit comprises a plurality of first measuring units, a thin film transistor arranged in each of the first measuring units, the thin film transistor being an N-type transistor and comprising a gate, a drain, and a source.

3. The array substrate of claim 2, wherein the gate signal start control line is arranged in the first measuring units and electrically connected with the gate and the drain of each thin film transistor, the source of each thin film transistor being electrically connected with a different one of the gate lines, the gate signal start control line comprising a third terminal being the first terminal of the temperature measuring unit, and a fourth terminal being the second terminal of the temperature measuring unit.

4. The array substrate of claim 2, wherein the temperature measuring unit further comprises a plurality of second measuring units, a thin film transistor array arranged in each of the second measuring units and comprising a first thin film transistor and a second thin film transistor, a gate of the first thin film transistor being the first terminal of the temperature measuring unit, a source of the first thin film transistor being electrically connected with one of the gate lines;

a drain of the second thin film transistor is the second terminal of the temperature measuring unit, and a gate of and the second thin film transistor being electrically connected with another one of the gate lines.

5. The array substrate of claim 4, wherein a drain of the first thin film transistor is electrically connected with a source of the second thin film transistor.

6. The array substrate of claim 4, wherein the thin film transistor array further comprises a third transistor.

7. The array substrate of claim 6, wherein a drain of the first thin film transistor is electrically connected with a source of the third thin film transistor, and a drain of the third thin film transistor is electrically connected with a source of the second thin film transistor.

8. The array substrate of claim 6, wherein the thin film transistor array further comprises a fourth thin film transistor, a drain of the first thin film transistor is electrically connected with the source of the third thin film transistor, a drain of the third thin film transistor is electrically connected with a source of the fourth thin film transistor, and a drain of the fourth thin film transistor is electrically connected with a source of the second thin film transistor.

9. The array substrate of claim 4, wherein each of the second measuring units comprises a plurality of serially connected thin film transistors.

10. The array substrate of claim 1, wherein each of the pixel units comprises a plurality of sub-pixels, one temperature measuring unit being arranged for every n sub-pixels, a width of the one temperature measuring unit is defined as W, a compression length of each sub-pixel is defined as a, W, n, and a satisfy the relations:

W≧

n×

3a, wherein n is a positive integer greater than or equal to 3; and

0.5 μ

m≦

a≦

2.5 μ

m.

11. The array substrate of claim 1, wherein the gate signal start line is a straight line, a broken line, or a wavy line.

12. A display panel comprising an array substrate and a color filter substrate arranged opposite to the array substrate, the color filter substrate comprising a color resist unit area arranged opposite to a pixel unit area on the array substrate, and a preset light shielding area arranged opposite to a temperature measuring unit on the array substrate;

wherein the array substrate comprises;

a substrate;

a plurality of gate lines and a plurality of data lines arranged on the substrate, the gate lines intersecting the data lines and being insulated from the data lines;

a plurality of pixel units arranged in an array and surrounded by the intersecting gate lines and the data lines;

a gate signal start control line;

a signal input line and a signal output line; and

a resistor is arranged on the signal input line;

wherein the temperature measuring unit comprises at least one thin film transistor, a first terminal electrically connected with the signal input line, and a second terminal electrically connected with the signal output line.

13. A display device comprising the display panel of claim 12, an integrated circuit (IC) and a flexible printed circuit board, wherein the IC or the flexible printed circuit board inputs a signal to the display panel through the signal input line, and the display panel returns an output signal to the IC or the flexible printed circuit board through the signal output line.