SEMICONDUCTOR DEVICE HAVING SUPER JUNCTION STRUCTURE, METHOD FOR MANUFACTURING THE SAME AND METHOD FOR MANUFACTURING SUPER JUNCTION STRUCTURE

• US 20160126307A1
• Filed: 12/30/2014
• Published: 05/05/2016
• Est. Priority Date: 11/04/2014
• Status: Abandoned Application

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: LI, Lian-Jie, CHEN, Zhong-Hao, HAN, Feng, ZHANG, Shuai, WU, Jian
• Application Number:
  US14/586,453
• Publication Number:
  US 20160126307A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/2253 by ion implantation
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device having a super junction structure includes a substrate, an epitaxial layer of a first conductivity type, a plurality of pillars of a second conductivity type, a plurality of gate trenches, an insulating layer and a plurality of doped wells of the second conductivity type. The epitaxial layer of the first conductivity type is on the substrate. The pillars of the second conductivity type are in the epitaxial layer, in which the second conductivity type is opposite to the first conductivity type. The gate trenches are individually corresponding to and over the pillars. The insulating layer is in the gate trenches. The doped wells of the second conductivity type are in the epitaxial layer, in which each of the doped wells is between two adjacent gate trenches. A method for manufacturing the semiconductor device and a method for manufacturing a super junction structure are also provided.

Claims

1. A semiconductor device having a super junction structure, comprising:

a substrate;

an epitaxial layer of a first conductivity type on the substrate;

a plurality of pillars of a second conductivity type in the epitaxial layer, wherein the second conductivity type is opposite to the first conductivity type;

a plurality of gate trenches individually correspond to and over the pillars;

an insulating layer in the gate trenches; and

a plurality of doped wells of the second conductivity type in the epitaxial layer, wherein each of the doped wells is between two adjacent gate trenches.

2. The semiconductor device of claim 1, wherein each of the pillars is a trench filled with the second conductivity type material or a multilayer structure.

3. The semiconductor device of claim 2, wherein the trench is an angled trench.

4. The semiconductor device of claim 2, wherein the trench has a same pattern as that of the gate trenches.

5. The semiconductor device of claim 2, wherein the multilayer structure is a multilayer of the second conductivity type.

6. The semiconductor device of claim 1, wherein the insulating layer comprises an oxide layer disposed on an inner surface of the gate trenches;

and a polymer material disposed on the oxide layer and in the gate trenches.

7. The semiconductor device of claim 1, wherein the pillars are individually in contact with the insulating layer in the gate trenches.

8. The semiconductor device of claim 1, further comprising a bury layer of the first conductivity type between the substrate and epitaxial layer.

9. A method for manufacturing a semiconductor device having a super junction structure, comprising:

forming an epitaxial layer on a substrate, wherein the epitaxial layer is a first conductivity type;

forming a doped layer in the epitaxial layer, wherein the doped layer is a second conductivity type opposite to the first conductivity type;

forming a plurality of gate trenches in the doped layer and the epitaxial layer;

forming a plurality of pillars in the epitaxial layer and individually correspond to and under the gate trenches; and

filling an insulating material in the gate trenches.

10. The method of claim 9, wherein forming the pillars comprises forming a trench filled with the second conductivity type material or forming a multilayer structure.

11. The method of claim 10, wherein forming the trench comprises forming an angled trench, and a second conductivity type material is filled in the trench by an epitaxial method.

12. The method of claim 10, wherein a pattern of the trench is formed the same as that of the gate trenches.

13. The method of claim 10, wherein forming the multilayer structure comprises forming a multilayer of the second conductivity type by performing an ion implantation.

14. The method of claim 9, wherein forming the insulating layer comprises forming an oxide layer on an inner surface of the gate trenches;

and filling a polymer material in the gate trenches.

15. The method of claim 9, further comprising forming a bury layer of the first conductivity type between the substrate and the epitaxial layer.

16. A method for manufacturing a super junction structure, comprising:

forming a plurality of trenches in a substrate of a first conductivity type;

forming a doped region of a second conductivity type in the substrate and surrounding the trenches, wherein the second conductivity type is opposite to the first conductivity type;

filling an undoped material in the trenches; and

forming a pillar of the second conductivity type from the undoped material in the trenches.

17. The method of claim 16, wherein forming the trenches comprises performing an etching method to form a plurality of angled trenches.

18. The method of claim 16, wherein forming the pillar of the second conductivity type comprises performing a thermal diffusion process to diffuse the doped region of the second conductivity type surrounding the trenches into the undoped material in the trenches, so as to form the pillar of the second conductivity type.

19. The method of claim 16, wherein filling the undoped material in the trenches comprises depositing an undoped polymer material in the trenches.

20. The method of claim 16, wherein the pillar of the second conductivity type is formed under a gate trench or a doped well of a second conductivity type.