S/D CONNECTION TO INDIVIDUAL CHANNEL LAYERS IN A NANOSHEET FET

• US 20160126310A1
• Filed: 10/21/2015
• Published: 05/05/2016
• Est. Priority Date: 10/30/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: OBRADOVIC, Borna, RODDER, Mark, HONG, Joon, KITTL, Jorge
• Granted Patent: US 9,653,287 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02603 Nanowires
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/28531 Making of side-wall contacts
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/41758 for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular H01L29/41733 - H01L29/4175 take precedence
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A field effect transistor (FET) and a method to form the FET are disclosed. The FET comprises a channel region comprising a nanosheet layer/sacrificial layer stack. The stack comprises at least one nanosheet layer/sacrificial layer pair. Each nanosheet layer/sacrificial layer pair comprises an end surface. A conductive material layer is formed on the end surface of the pairs, and a source/drain contact is formed on the conductive material layer. In one embodiment, the sacrificial layer of at least one pair further may comprise a low-k dielectric material proximate to the end surface of the pair. A surface of the low-k dielectric material proximate to the end surface of the pair is in substantial alignment with the end surface of the nanosheet layer. Alternatively, the surface of the low-k dielectric material proximate to the end surface of the pair is recessed with respect to the end surface of the nanosheet layer.

Claims

1. A method to form a semiconductor device, the method comprising:

forming a nanosheet layer/sacrificial layer stack comprising at least one nanosheet layer/sacrificial layer pair, each nanosheet layer/sacrificial layer pair comprising a top surface, a bottom surface, a first end surface and a second end surface, the top surface of the pair being opposite the bottom surface and the first end surface of the pair being opposite the second end surface, the nanosheet layer being on one side of the pair and the sacrificial layer being on an opposing side of the pair, the nanosheet layer comprising a first thickness at the first end surface of the pair, the sacrificial layer comprising a second thickness at the first end surface of the pair, and the first thickness and the second thicknesses both being measured in a direction that is between the top surface and the bottom surface of the pair;

forming a first conductive material layer comprising a first surface and a second surface, the first surface of the first conductive material layer being formed on the first end surface of the each pair of the stack, and the second surface of the first conductive material layer being opposite the first surface of the first conductive material layer; and

forming a source/drain contact on the second surface of the first conductive material layer.

2. The method according to claim 1, further comprising before forming the source/drain contact on the second surface of the first conductive material layer, forming a second conductive material layer comprising a first surface and a second surface, the first surface of the second conductive material layer being formed on the second surface of the first conductive material layer, and

wherein forming the source/drain contact on the second surface of the first conductive material layer comprises forming the source/drain contact on the second surface of the second conductive material layer.

3. The method according to claim 2, further comprising reacting the second conductive material layer with the first conductive material layer to form a salicide.

4. The method according to claim 1, wherein the first conductive material layer is formed by deposition.

5. The method according to claim 1, wherein the first conductive material layer comprises a polycrystalline or an amorphous conductive material, a semiconductor material, a metallic material, or a combination thereof.

6. The method according to claim 1, wherein the first conductive material layer comprises at least in part Ti, Co, Ni, Pt, Ta, Mo, W, a metallic nitrided alloy, or a metallic nitrided silicide.

7. The method according to claim 1, further comprising before forming the first conductive material layer on the first end surface of the stack:

removing a predetermined amount of the sacrificial layer from the first end surface of the sacrificial layer of at least one pair to form a first space associated with the pair; and

forming a low-k dielectric material in each first space so that a surface of the low-k dielectric material proximate to the first end surface of the pair is in substantial alignment with the first end surface of the nanosheet layer.

8. The method according to claim 7, further comprising reacting the second conductive material layer with the first conductive material layer to form a salicide.

9. The method according to claim 1, further comprising before forming the first conductive material layer on the first end surface of the stack:

removing a predetermined amount of the sacrificial layer from the first end surface of the sacrificial layer of at least one pair to form a first space associated with the pair; and

forming a low-k dielectric material in each first space so that a surface of the low-k dielectric material proximate to the first end surface of the pair is recessed toward the second end surface of the pair from the first end surface of the nanosheet layer of the pair.

10. The method according to claim 1, wherein the semiconductor device comprises a nanosheet field effect transistor (FET) of a first conductivity type or nanosheet FET of a second conductivity type, the first conductivity type being opposite from the second conductivity type.

11. A field effect transistor (FET), comprising:

a channel region comprising a nanosheet layer/sacrificial layer stack, the nanosheet layer/sacrificial layer stack comprising at least one nanosheet layer/sacrificial layer pair, each nanosheet layer/sacrificial layer pair comprising a top surface, a bottom surface, a first end surface and a second end surface, the top surface of the pair being opposite the bottom surface and the first end surface of the pair being opposite the second end surface, the nanosheet layer being on one side of the pair and the sacrificial layer being on an opposing side of the pair, the nanosheet layer comprising a first thickness at the first end surface of the pair, the sacrificial layer comprising a second thickness at the first end surface of the pair, and the first thickness and the second thicknesses both being measured in a direction that is between the top surface and the bottom surface of the pair;

a conductive material layer comprising a first surface and a second surface, the first surface of the conductive material layer being formed on the first end surface of each pair of the stack, and the second surface of the conductive material layer being opposite the first surface of the conductive material layer; and

a source/drain contact formed on the second surface of the conductive material layer.

12. The FET according to claim 11, wherein the conductive material layer comprises at least in part a salicide.

13. The FET according to claim 11, wherein the conductive layer comprises a polycrystalline or an amorphous conductive material, a semiconductor material, a metallic material, or a combination thereof.

14. The FET according to claim 11, wherein the conductive layer comprises at least in part Ti, Co, Ni, Pt, Ta, Mo, W, a metallic nitrided alloy, or a metallic nitrided silicide.

15. The FET according to claim 11, wherein a portion of the sacrificial layer of at least one nanosheet layer/sacrificial layer pair further comprises a low-k dielectric material proximate to the first end surface of the pair, and

wherein a surface of the low-k dielectric material proximate to the first end surface of the pair is in substantial alignment with the first end surface of the nanosheet layer.

16. The FET according to claim 11, wherein a portion of the sacrificial layer of at least one nanosheet layer/sacrificial layer pair further comprises a low-k dielectric material proximate to the first end surface of the pair, and

wherein a surface of the low-k dielectric material proximate to the first end surface of the pair is recessed toward the second end surface of the pair from the first end surface of the nanosheet layer.

17. A field effect transistor (FET), comprising:

a first source/drain (S/D) region;

a second S/D region; and

a channel region disposed between the first S/D region and the second S/D region, the channel region comprising;

a plurality of nanosheet layer/sacrificial layer pairs formed on each other, each nanosheet layer/sacrificial layer pair comprising;

a top surface, a bottom surface, a first end surface and a second end surface, the top surface being opposite the bottom surface and the first end surface being opposite the second end surface, the nanosheet layer being on one side of the pair and the sacrificial layer being on an opposing side of the pair, the nanosheet layer comprising a first thickness at the first end surface of the pair and a second thickness at the second end surface of the pair, the sacrificial layer comprising a third thickness at the first end surface of the pair and a fourth thickness at the second end surface of the pair, and the first, second, third and fourth thicknesses being measured in a direction that is between the top surface and the bottom surface of the pair, and

a first conductive material layer comprising a first surface and a second surface, the first surface of the first conductive material layer being formed on the first end surface of each of the plurality of pairs, and the second surface of the first conductive material layer being opposite the first surface of the first conductive material layer and being coupled to the first source/drain region.

18. The FET according to claim 17, wherein a portion of the sacrificial layer of at least one nanosheet layer/sacrificial layer pair further comprises a low-k dielectric material proximate to the first end surface of the pair, and

wherein a surface of the low-k dielectric material proximate to the first end of the pair is in substantial alignment with the first end surface of the nanosheet layer.

19. The FET according to claim 17, wherein a portion of the sacrificial layer of at least one nanosheet layer/sacrificial layer pair further comprises a low-k dielectric material proximate to the first end surface of the pair, and

wherein a surface of the low-k dielectric material proximate to the first end of the pair is recessed toward the second end surface of the pair from the first end surface of the nanosheet layer.

20. The FET according to claim 17, wherein the channel region further comprises a second conductive material layer comprising a first surface and a second surface, the first surface of the second conductive material layer being formed on the second end surface of each of the plurality of pairs, and the second surface of the second conductive material layer being opposite the first surface of the second conductive material layer and being coupled to the second source/drain region.