LIQUID CRYSTAL DISPLAY PANEL AND BLACK PICTURE INSERTION METHOD FOR THE PANEL DISPLAYED IN 3D MODE

• US 20160127720A1
• Filed: 11/10/2014
• Published: 05/05/2016
• Est. Priority Date: 10/31/2014
• Status: Active Grant

• Current Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Original Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Inventors: Zhu, Jiang
• Granted Patent: US 9,564,093 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G09G 2310/0205 Simultaneous scanning of several lines in flat panels
• CPC Class Codes: G09G 2310/0213 controlling the sequence of the scanning lines with respect to the patterns to be displayed, e.g. to save power
• CPC Class Codes: G09G 2310/0251 Precharge or discharge of pixel before applying new pixel voltage
• CPC Class Codes: G09G 2310/0283 Arrangement of drivers for different directions of scanning
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/003 to produce spatial visual effects
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: H04N 13/341 using temporal multiplexing

Abstract

An LCD panel includes multiple data lines, multiple scanning lines, multiple pixels, and multiple control transistors. Each pixel connected with a corresponding one of the data lines and one of the scanning lines. Gate electrodes of the control transistors are connected with a same scanning line. A source electrode of each control transistor is connected with a corresponding one of the data lines. Drain electrodes of the control transistors are connected with each other. A black picture insertion method for the LCD panel displayed in a 3D mode is also disclosed. Accordingly, a refresh frequency of the driving circuit is one half of the prior art. The power consumption and cost are reduced. Besides, a black picture is inserted into one frame during a blank time domain of the one frame such that the brightness is increased and the charge time of the liquid crystal capacitor is increased.

Claims

1. A liquid crystal display panel, comprising:

multiple data lines;

multiple scanning lines;

multiple pixels, each pixel connected with a corresponding one of the data lines and a corresponding one of the scanning lines; and

multiple control transistors;

wherein, a gate electrode of each control transistor is connected with a same scanning line;

a source electrode of each control transistor is connected with a corresponding one of the data lines;

each of the control transistors has a drain electrode, and the drain electrodes are connected with each other.

2. The liquid crystal display panel according to claim 1, wherein, each of the multiple pixels comprises a pixel transistor, a storage capacitor, and a liquid crystal capacitor;

a gate electrode of each pixel transistor is connected with a corresponding one of the scanning lines;

a source electrode of each pixel transistor is connected with a corresponding one of the data lines;

terminals of each storage capacitor and each liquid crystal capacitor are both connected with a drain electrode of each pixel transistor;

the other terminals of each storage capacitor and each liquid crystal capacitor are both connected with a common electrode.

3. The liquid crystal display panel according to claim 1, wherein, the drain electrode of each control transistor connects with a common electrode.

4. The liquid crystal display panel according to claim 2, wherein, the drain electrode of each control transistor connects with the common electrode.

5. The liquid crystal display panel according to claim 1, wherein, in a blank time domain of a (2n)th frame, the multiple control transistors and the multiple pixel transistors are all turned on, wherein, n is a positive integer.

6. The liquid crystal display panel according to claim 5, wherein, a scanning sequence of a (2n−

1)th frame and a scanning sequence of a (2n)th frame are inverse.

7. The liquid crystal display panel according to claim 1, wherein, in a blank time domain of an nth frame, the multiple control transistors and the multiple pixel transistors are all turned on, wherein, n is a positive integer.

8. The liquid crystal display panel according to claim 7, wherein, a scanning sequence of the nth frame and a scanning sequence of a (n+1)th frame are the same;

a scanning sequence of a (n+2)th frame and a scanning sequence of a (n+3)th frame are the same;

a scanning sequence of a (n+1)th frame and a scanning sequence of a (n+2)th frame are inverse.

9. A black picture insertion method for a liquid crystal display panel when displaying in a three-dimension (3D) mode, wherein, the liquid crystal display panel includes:

multiple data lines;

multiple scanning lines;

multiple pixels, each pixel connected with a corresponding one of the data lines and a corresponding one of the scanning lines; and

multiple control transistors;

wherein a gate electrode of each control transistor is connected with a same scanning line;

a source electrode of each control transistor is connected with a corresponding one of the data lines;

each of the control transistors has a drain electrode, and the drain electrodes are connected with each other; and

wherein, the black picture insertion method comprises;

turning on all of the control transistors and pixel transistors in a blank time domain of a (2n)th frame, wherein, n is a positive integer.

10. The black picture insertion method according to claim 9, wherein each of the multiple pixels comprises a pixel transistor, a storage capacitor, and a liquid crystal capacitor;

a gate electrode of each pixel transistor is connected with a corresponding one of the scanning lines;

a source electrode of each pixel transistor is connected with a corresponding one of the data lines;

terminals of each storage capacitor and each liquid crystal capacitor are both connected with a drain electrode of each pixel transistor;

the other terminals of each storage capacitor and each liquid crystal capacitor are both connected with a common electrode.

11. The black picture insertion method according to claim 9, wherein, the drain electrode of each control transistor connects with the common electrode.

12. The black picture insertion method according to claim 9, wherein, a scanning sequence of a (2n−

1)th frame and a scanning sequence of the (2n)th frame are inverse.

13. The black picture insertion method according to claim 10, wherein, a scanning sequence of a (2n−

1)th frame and a scanning sequence of a (2n)th frame are inverse.

14. The black picture insertion method according to claim 10, wherein, a scanning sequence of a (2n−

1)th frame and a scanning sequence of the (2n)th frame are inverse.

15. A black picture insertion method for a liquid crystal display panel when displaying in a three-dimension (3D) mode, wherein, the liquid crystal display panel includes:

multiple data lines;

multiple scanning lines;

multiple pixels, each pixel connected with a corresponding one of the data lines and a corresponding one of the scanning lines; and

multiple control transistors;

wherein a gate electrode of each control transistor is connected with a same scanning line;

a source electrode of each control transistor is connected with a corresponding one of the data lines;

each of the control transistors has a drain electrode, and the drain electrodes are connected with each other; and

wherein, the black picture insertion method comprises;

turning on all of the control transistors and pixel transistors in a blank time domain of an nth frame, wherein, n is a positive integer.

16. The black picture insertion method according to claim 15, wherein each of the multiple pixels comprises a pixel transistor, a storage capacitor, and a liquid crystal capacitor;

a gate electrode of each pixel transistor is connected with a corresponding one of the scanning lines;

a source electrode of each pixel transistor is connected with a corresponding one of the data lines;

terminals of each storage capacitor and each liquid crystal capacitor are both connected with a drain electrode of each pixel transistor;

the other terminals of each storage capacitor and each liquid crystal capacitor are both connected with a common electrode.

17. The black picture insertion method according to claim 15, wherein, the drain electrode of each control transistor connects with a common electrode.

18. The black picture insertion method according to claim 15, wherein, a scanning sequence of a nth frame and a scanning sequence of a (n+1)th frame are the same;

a scanning sequence of a (n+2)th frame and a scanning sequence of a (n+3)th frame are the same;

a scanning sequence of a (n+1)th frame and a scanning sequence of a (n+2)th frame are inverse.

19. The black picture insertion method according to claim 16, wherein, a scanning sequence of the nth frame and a scanning sequence of a (n+1)th frame are the same;

a scanning sequence of a (n+2)th frame and a scanning sequence of a (n+3)th frame are the same;

a scanning sequence of the (n+1)th frame and a scanning sequence of the (n+2)th frame are inverse.

20. The black picture insertion method according to claim 17, wherein, a scanning sequence of the nth frame and a scanning sequence of a (n+1)th frame are the same;

a scanning sequence of a (n+2)th frame and a scanning sequence of a (n+3)th frame are the same;

a scanning sequence of the (n+1)th frame and a scanning sequence of the (n+2)th frame are inverse.