RECOVERING STRANDED DATA

• US 20160132413A1
• Filed: 07/30/2013
• Published: 05/12/2016
• Est. Priority Date: 07/30/2013
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Wheeler, Andrew R., Lesartre, Gregg B.
• Granted Patent: US 10,152,399 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/2025 using centralised failover control functionality
• CPC Class Codes: G06F 11/203 using migration
• CPC Class Codes: G06F 11/2035 without idle spare hardware
• CPC Class Codes: G06F 11/2097 maintaining the standby controller/processing unit updated initialisation or re-synchronisation thereof G06F11/1658 and subgroups
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices

Abstract

A system and method for recovering stranded data from a non-volatile memory is provided. An example of a method includes copying data from a non-volatile memory (NVM) in a home node over a sideband interface and writing the data to a target memory region, wherein the target memory region is in a fail-over node.

Claims

1. A method for recovering stranded data, comprising:

copying data from a non-volatile memory (NVM) in a home node over a sideband interface; and

writing the data to a target memory region, wherein the target memory region is in a fail-over node.

2. The method of claim 1, further comprising writing the data to a second NVM in the fail-over node.

3. The method of claim 1, further comprising writing the data to a virtual memory area in the fail-over node.

4. The method of claim 1, further comprising accessing the NVM in the home node from a management subsystem.

5. The method of claim 1, further comprising accessing the first NVM when main system power is off to the home node.

6. The method of claim 1, further comprising providing a backup power in case all power has failed in the home node.

7. The method of claim 1, further comprising reactivating processes in the target memory region.

8. The method of claim 1, further comprising:

migrating a plurality of memory stripes from a corresponding plurality of NVMs in the home node to the failover node;

detecting if any of the plurality of memory stripes comprises missing or defective data; and

rebuilding the missing or defective data.

9. A computing system, comprising:

a home node, comprising;

a processor;

a memory controller coupled to the processor;

a main network interface coupled to the processor, and a network;

a non-volatile memory (NVM) coupled to the memory controller; and

a system management device, coupled to the memory controller, the processor, and a system management network; and

a fail-over node, comprising

a processor;

a memory controller coupled to the processor;

a main network interface coupled to the processor, and to the network;

a target memory region coupled to the memory controller; and

a system management device, coupled to the memory controller, the processor, and the system management network;

wherein the system management network can access data stored in the NVM of the home node through the system management device in the home node, and transfer the data to the target memory region of the fail-over node through the system management device of the fail-over node.

10. The computing system of claim 9, wherein the system management device in the home node detects a failure in the home node prior to transferring the data from the NVM of the home node to the target memory region.

11. The computing system of claim 9, wherein the system management device in the home node comprises a back-up power driver to power the memory controller in case of a complete failure of the system power in the home node.

12. The computing system of claim 9, wherein the system management device in the home node comprises:

a processor;

a memory comprising instructions, wherein the instructions;

direct the processor to detect a failure of the home node;

access data in the NVM; and

transfer the data to a target memory region in the fail-over node.

13. The computing system of claim 9, wherein the system management network comprises a management server that monitors operation of a plurality of nodes and identifies a fail-over node for any of a plurality of nodes that fail.

14. A tangible, non-transitory, machine-readable medium comprising instructions to direct a processor to:

detect a failure of a home node;

access data in the NVM; and

transfer the data to a target memory region in a fail-over node.

15. The tangible, non-transitory, machine-readable medium of claim 14, comprising instructions to reactivate processes in the fail-over node.