Memory Control Circuit and Processor
First Claim
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1. A memory control circuit comprising:
- a request determination circuitry to determine whether a period without read-out request and write request to an i-th (i being an integer of 1 or more and of n or less, n being an integer of 2 or more) level cache memory among first to n-th level cache memories continues for a first period of time or longer, the i-th level cache memory comprising a first non-volatile memory; and
a power-supply controller to control a power cut-off timing to the i-th level cache memory based on a determination of the request determination circuitry.
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Abstract
A memory control circuit has a request determination circuitry to determine whether a period without read-out request and write request to an i-th (i being an integer of 1 or more and of n or less, n being an integer of 2 or more) level cache memory among first to n-th level cache memories continues for a first period of time or longer, the i-th level cache memory comprising a first nonvolatile memory, and a power-supply controller to control a power cut-off timing to the i-th level cache memory based on a determination of the request determination circuitry.
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Citations
20 Claims
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1. A memory control circuit comprising:
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a request determination circuitry to determine whether a period without read-out request and write request to an i-th (i being an integer of 1 or more and of n or less, n being an integer of 2 or more) level cache memory among first to n-th level cache memories continues for a first period of time or longer, the i-th level cache memory comprising a first non-volatile memory; and a power-supply controller to control a power cut-off timing to the i-th level cache memory based on a determination of the request determination circuitry. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A processor comprising:
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a processor core; and a memory control circuit to control an access to a cache memory in accordance with instruction from the processor core, wherein the memory control circuit comprises; a request determination circuitry to determine whether a period without read-out request and write request to an i-th (i being an integer of 1 or more and of n or less, n being an integer of 2 or more) level cache memory among first to nth level cache memories continues for a first period of time or longer, the i-th level cache memory comprising a first non-volatile memory; and a power-supply controller to control a power cut-off timing to the i-th level cache memory based on a determination of the request determination circuitry. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20)
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Specification