ALUMINUM OXIDE LANDING LAYER FOR CONDUCTIVE CHANNELS FOR A THREE DIMENSIONAL CIRCUIT DEVICE

• US 20160133640A1
• Filed: 07/11/2014
• Published: 05/12/2016
• Est. Priority Date: 07/11/2014
• Status: Active Grant

• Current Assignee: Intel NDTM US LLC (Intel Corporation)
• Original Assignee: Fatma A. Simsek-Ege, Gordon A. Haller, Hongbin Zhu
• Inventors: ZHU, HONGBIN, HALLER, GORDON A., SIMSEK-EGE, FATMA A.
• Granted Patent: US 9,595,531 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/50 characterised by the boundary region between the core region and the peripheral circuit region
• CPC Class Codes: H10B 41/60 the control gate being a doped region, e.g. single-poly memory cell

Abstract

A multitier stack of memory cells having an aluminum oxide (AlOx) layer as a noble HiK layer to provide etch stop selectivity. Each tier of the stack includes a memory cell device. The circuit includes a source gate select polycrystalline (SGS poly) layer adjacent the multitier stack of memory cells, wherein the SGS poly layer is to provide a gate select signal for the memory cells of the multitier stack. The circuit also includes a conductive source layer to provide a source conductor for a channel for the tiers of the stack. The AlOx layer is disposed between the source layer and the SGS poly layer and provides both dry etch selectivity and wet etch selectivity for creating a channel to electrically couple the memory cells to the source layer.

Claims

1. A circuit device comprising:

a multitier stack of memory cells, each tier of the stack including a memory cell device;

a source gate select polycrystalline (SGS poly) layer adjacent the multitier stack of memory cells, the SGS poly layer to provide a gate select signal for the memory cells of the multitier stack;

a conductive source layer to provide a source conductor for a channel for the tiers of the stack; and

an aluminum oxide (AlOx) layer between the source layer and the SGS poly layer, the AlOx layer providing an etch stop layer to separate the SGS poly layer from the source layer, wherein the AlOx layer provides both dry etch selectivity and wet etch selectivity, wherein a channel etch etches through the multitier stack of memory cells and the SGS poly layer, and stops at the AlOx layer and does not expose the source layer, and wherein a selective gate etch etches gate contacts in the memory cells and etches the AlOx layer to expose the source layer.

2. The circuit device of claim 1, wherein the SGS poly layer comprises a p-type doped polysilicon.

3. The circuit device of claim 1, wherein the source layer includes one or more of tungsten silicide, heavily doped polysilicon, or poly-tungsten silicide.

4. The circuit device of claim 1, wherein the source layer comprises an n-type doped polysilicon.

5. The circuit device of claim 1, wherein the AlOx layer further comprises:

a floating gate triggered by the gate select signal to provide current from the source layer to the multitier stack of memory cells.

6. The circuit device of claim 5, wherein the channel comprises a hollow channel extending through the multitier stack, the hollow channel including conductive material surrounding a channel insulator to provide electrical contact to gates of the memory cells;

wherein the AlOx layer floating gate provides current from the source layer to the hollow channel.

7. The circuit device of claim 1, further comprising:

an oxide layer between the AlOx layer and the SGS poly layer.

8. The circuit device of claim 1, further comprising:

an oxide layer between the AlOx layer and the source layer.

9. An electronic device comprising:

a three-dimensional stacked memory device to store data, the memory device including;

a multitier stack of memory cells, each tier of the stack including a memory cell device;

a source gate select polycrystalline (SGS poly) layer adjacent the multitier stack of memory cells, the SGS poly layer to provide a gate select signal for the memory cells of the multitier stack;

a conductive source layer to provide a source conductor for a channel for the tiers of the stack; and

an aluminum oxide (AlOx) layer between the source layer and the SGS poly layer, the AlOx layer providing an etch stop layer to separate the SGS poly layer from the source layer, wherein the AlOx layer provides both dry etch selectivity and wet etch selectivity, wherein a channel etch etches through the multitier stack of memory cells and the SGS poly layer, and stops at the AlOx layer and does not expose the source layer, and wherein a selective gate etch etches gate contacts in the memory cells and etches the AlOx layer to expose the source layer; and

a high-definition display coupled to generate a display based on data stored in the memory device.

10. The electronic device of claim 9, wherein the source layer includes one or more of tungsten silicide, heavily doped polysilicon, or poly-tungsten silicide.

11. The electronic device of claim 9, wherein the AlOx layer further comprises:

a floating gate triggered by the gate select signal to provide current from the source layer to the multitier stack of memory cells.

12. The electronic device of claim 11, wherein the channel comprises a hollow channel extending through the multitier stack, the hollow channel including conductive material surrounding a channel insulator to provide electrical contact to gates of the memory cells;

wherein the AlOx layer floating gate provides current from the source layer to the hollow channel.

13. The electronic device of claim 9, wherein the memory device further comprises:

an oxide layer between the AlOx layer and the SGS poly layer.

14. The electronic device of claim 9, wherein the memory device further comprises:

an oxide layer between the AlOx layer and the source layer.

15. A method comprising:

generating a multitier stack of memory cells, each tier of the stack including a memory cell device;

creating a source gate select polycrystalline (SGS poly) layer adjacent the multitier stack of memory cells, the SGS poly layer to provide a gate select signal for the memory cells of the multitier stack;

creating a conductive source layer on a semiconductor substrate to provide a source conductor for a channel for the tiers of the stack; and

creating an aluminum oxide (AlOx) layer between the source layer and the SGS poly layer, the AlOx layer providing an etch stop layer to separate the SGS poly layer from the source layer, wherein the AlOx layer provides both dry etch selectivity and wet etch selectivity, wherein a channel etch etches through the multitier stack of memory cells and the SGS poly layer, and stops at the AlOx layer and does not expose the source layer, and wherein a selective gate etch etches gate contacts in the memory cells and etches the AlOx layer to expose the source layer.

16. The method of claim 15, wherein creating the source layer comprises creating a source layer that includes one or more of tungsten silicide, heavily doped polysilicon, or poly-tungsten silicide.

17. The method of claim 15, wherein creating the AlOx layer further comprises creating a floating gate to be triggered by the gate select signal to provide current from the source layer to the multitier stack of memory cells.

18. The method of claim 17, further comprising creating a hollow channel extending through the multitier stack, the hollow channel including conductive material surrounding a channel insulator to provide electrical contact to gates of the memory cells;

wherein the AlOx layer floating gate provides current from the source layer to the hollow channel.

19. The method of claim 15, further comprising creating an oxide layer between the AlOx layer and the SGS poly layer.

20. The method of claim 15, further comprising creating an oxide layer between the AlOx layer and the source layer.