SIGNAL INTEGRITY IN MUTLI-JUNCTION TOPOLOGIES

• US 20160134036A1
• Filed: 11/12/2014
• Published: 05/12/2016
• Est. Priority Date: 11/12/2014
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: HUANG, Shaowu, UMOH, Ifiok J., LEE, Beom-Taek, XIAO, Kai
• Application Number:
  US14/539,597
• Publication Number:
  US 20160134036A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 13/4086 Bus impedance matching, e.g. termination

Abstract

A channel (e.g., memory channel) coupling a processor to multiple devices (e.g., DIMMs) is described. The channel has an interconnect topology with multiple interconnect portions coupled together with two or more junctions. At least one of these junctions has first and second interconnect portions that cross each other to form a plus-shaped junction. Also, the interconnect routing between the two or more junctions has an impedance matched to impedance of the two or more junctions.

Claims

1. A system comprising:

a processor;

a plurality of devices; and

a channel coupling the processor to the plurality of devices, the channel having an interconnect topology with a plurality of interconnect portions coupled together with two or more junctions, at least one of the two or more junctions having first and second interconnect portions that cross each other to form a plus-shaped junction, and wherein interconnect routing between the two or more junctions having an impedance matched to impedance of the two or more junctions.

2. The system defined in claim 1 wherein first and second interconnect portions of the plus-shaped junction are perpendicular to each other.

3. The system defined in claim 1 wherein the first interconnect portion of the plus-shaped junction is connected to a third interconnect portion at a slot for one of the devices.

4. The system defined in claim 3 wherein the one device is closest in the channel to the processor.

5. The system defined in claim 3 wherein the plurality of devices comprises three devices and the one device is between two of the three devices.

6. The system defined in claim 1 wherein the plus-shaped junction is located between two of the plurality of devices closest in the channel to the processor.

7. The system defined in claim 1 wherein routing length of an interconnect routing between two junctions of the two or more junctions is set based on resonance frequency of the interconnect routing between the two junctions, effective relative permittivity of the interconnect routing, and electromagnetic wave speed.

8. The system defined in claim 1 wherein interconnect routing between the two or more junctions has an impedance matched to impedance of the two or more junctions by at least one of:

increasing routing width of the interconnect routing;

reducing routing dielectric thickness of the interconnect routing; and

increasing routing dielectric constant of the interconnect routing.

9. The system defined in claim 1 wherein the topology includes a staggered transition via in which a first interconnect portion connecting a second interconnect portion, which is connected to the processor, to a third interconnect portion, which is connected to a first set of devices, is connected at a location at the second interconnect portion away from being directly below any of the first set of devices.

10. The system defined in claim 9 wherein the first interconnect portion of the staggered transition via is connected to the second interconnect portion at a location between two devices in the first set of devices.

11. The system defined in claim 9 wherein the second interconnect portion is coupled to one or more to a first set of devices via micro-vias.

12. The system defined in claim 9 wherein the first set of devices comprises a plurality of DIMMs.

13. The system defined in claim 9 wherein the third interconnect comprises a stripline or microstrip.

14. The system defined in claim 1 wherein the channel comprises a memory channel with multiple slots for interfacing to DDR memory devices.

15. A channel for using in providing communication between a processor and a plurality of devices, the channel having an interconnect topology with a plurality of interconnect portions coupled together with two or more junctions, at least one of the two or more junctions having first and second interconnect portions that cross each other to form a plus-shaped junction, and wherein interconnect routing between the two or more junctions having an impedance matched to impedance of the two or more junctions.

16. The channel defined in claim 15 wherein first and second interconnect portions of the plus-shaped junction are perpendicular to each other.

17. The channel defined in claim 15 wherein the first interconnect portion of the plus-shaped junction is connected to a third interconnect portion at a slot for one of the devices, and wherein the one device is closest in the channel to the processor or is between two of three devices.

18. The channel defined in claim 15 wherein the plus-shaped junction is located between two of the plurality of devices closest in the channel to the processor.

19. The channel defined in claim 15 wherein interconnect routing between the two or more junctions has an impedance matched to impedance of the two or more junctions by at least one of:

increasing routing width of the interconnect routing;

reducing routing dielectric thickness of the interconnect routing; and

increasing routing dielectric constant of the interconnect routing.

20. The channel defined in claim 15 wherein the topology includes a staggered transition via in which a first interconnect portion connecting a second interconnect portion, which is connected to the processor, to a third interconnect portion, which is connected to a first set of devices, is connected at a location at the second interconnect portion away from being directly below any of the first set of devices.

21. The channel defined in claim 20 wherein the first interconnect portion of the staggered transition via is connected to the second interconnect portion at a location between two devices in the first set of devices.

22. A method to reduce multiple reflections between junctions in a channel having an interconnect topology, the method comprising:

communicating information from a processor and one or more of a plurality of devices using a channel; and

communicating information to the processor from one or more of a plurality of devices using the channel, wherein the channel has an interconnect topology with a plurality of interconnect portions coupled together with two or more junctions, at least one of the two or more junctions having first and second interconnect portions that cross each other to form a plus-shaped junction, and wherein interconnect routing between the two or more junctions having an impedance matched to impedance of the two or more junctions.

23. The method defined in claim 22 wherein first and second interconnect portions of the plus-shaped junction are perpendicular to each other.

24. The method defined in claim 22 wherein the first interconnect portion of the plus-shaped junction is connected to a third interconnect portion at a slot for one of the devices, and wherein the one device is closest in the channel to the processor, is between two of three devices, or is located between two of the plurality of devices closest in the channel to the processor.

25. The method defined in claim 22 wherein the topology includes a staggered transition via in which a first interconnect portion connecting a second interconnect portion, which is connected to the processor, to a third interconnect portion, which is connected to a first set of devices, is connected at a location at the second interconnect portion away from being directly below any of the first set of devices.