COMPLETELY UTILIZING HAMMING DISTANCE FOR SECDED BASED ECC DIMMS

• US 20160134307A1
• Filed: 03/05/2015
• Published: 05/12/2016
• Est. Priority Date: 11/06/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: NAIR, Prashant Jayaprakash, HU, Chaohong, ZHENG, Hongzhong
• Granted Patent: US 9,754,684 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: H03M 13/19 Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes

Abstract

In an Error Correction Code (ECC)-based memory, a Single Error Correction Double Error Detection (SECDED) scheme is used with data aggregation to correct more than one error in a memory word received in a memory burst. By completely utilizing the Hamming distance of the SECDED (128,120) code, 8 ECC bits can potentially correct one error in 120 data bits. Each memory burst is effectively “expanded” from its actual 64 data bits to 120 data bits by “sharing” additional 56 data bits from all of the other related bursts. When a cache line of 512 bits is read, the SECDED (128,120) code is used in conjunction with all the received 64 ECC bits to correct more than one error in the actual 64 bits of data in a memory word. The data mapping of the present disclosure translates to a higher rate of error correction than the existing (72,64) SECDED code.

Claims

1. A method comprising:

receiving a burst-specific content from each burst in a plurality of bursts from a memory module, wherein the burst-specific content includes a first pre-determined number of bits of burst-specific data along with corresponding bits of burst-specific Error Correcting Code (ECC);

storing the burst-specific content from each burst in the plurality of bursts; and

using all received ECC bits as part of a Single Error Correction Double Error Detection (SECDED) code to correct more than one error in the first pre-determined number of bits of burst-specific data from at least one of the plurality of bursts.

2. The method of claim 1, wherein the SECDED code is a SECDED (128,120) code.

3. The method of claim 1, wherein the corresponding bits of burst-specific ECC include 8 bits of burst-specific ECC, and wherein using all received ECC bits as part of the SECDED code includes:

for each burst in the plurality of bursts, selecting a burst-specific second pre-determined number of bits of data from all other bursts in the plurality of bursts, wherein a total of the first pre-determined number of bits and the second pre-determined number of bits is at least 120; and

for each burst in the plurality of bursts, applying the 8 bits of burst-specific ECC to the corresponding first pre-determined number of bits of burst-specific data as well as to the burst-specific second pre-determined number of bits of data.

4. The method of claim 3, wherein selecting the burst-specific second pre-determined number of bits of data includes:

for each burst in the plurality of bursts, selecting an identical number of bits from the burst-specific data associated with each of the other bursts to generate the second pre-determined number of bits of data.

5. The method of claim 1, wherein the plurality of bursts is eight bursts.

6. The method of claim 1, wherein the first pre-determined number of bits is 64 bits.

7. The method of claim 1, wherein the memory module is an ECC Dual In-line Memory Module (ECC-DIMM).

8. The method of claim 1, further comprising:

receiving a data content to be stored in the memory module through a plurality of successive memory accesses;

dividing the data content into a plurality of access-specific data, wherein each access-specific data contains the first pre-determined number of bits;

for each access-specific data, selecting an additional second pre-determined number of bits of data from all other access-specific data in the plurality of access-specific data, wherein a total of the first pre-determined number of bits and the second pre-determined number of bits is at least 120;

for each memory access, applying the SECDED code to a combination of the access-specific data and associated additional second pre-determined number of bits of data to determine access-specific 8 bits of ECC; and

during each successive memory access, storing the access-specific data along with the access-specific 8 bits of ECC in the memory module.

9. The method of claim 8, wherein the plurality of successive memory accesses is eight accesses.

10. The method of claim 8, wherein selecting the additional second pre-determined number of bits of data includes:

for each access-specific data, selecting an identical number of bits from each of the other access-specific data to generate the additional second pre-determined number of bits of data.

11. A memory controller comprising:

a control unit;

a buffer coupled to the control unit, wherein the buffer is operative by the control unit to;

receive a burst-specific content from each burst in a plurality of bursts from a memory module, wherein the burst-specific content includes a pre-determined number of bits of burst-specific data along with corresponding bits of burst-specific Error Correcting Code (ECC), and

store the burst-specific content from each burst in the plurality of bursts; and

a decoder unit coupled to the buffer and the control unit, wherein the decoder unit is operative by the control unit to;

use all received ECC bits as part of a Single Error Correction Double Error Detection (SECDED) (128,120) code to correct more than one error in the pre-determined number of bits of burst-specific data from at least one of the plurality of bursts.

12. The memory controller of claim 11, wherein the corresponding bits of burst-specific ECC include 8 bits of burst-specific ECC, and, wherein, for each burst in the plurality of bursts, the control unit is operative to:

select an identical number of bits from the burst-specific data associated with each of the other bursts to generate a burst-specific additional 56 bits of data, wherein a total of the pre-determined number of bits and the additional 56 bits is at least 120, and

wherein, for each burst in the plurality of bursts, the decoder is further operative by the control unit to;

apply the 8 bits of burst-specific ECC to the corresponding pre-determined number of bits of burst-specific data as well as to the burst-specific additional 56 bits of data.

13. The memory controller of claim 11, wherein the pre-determined number of bits is 64 bits.

14. The memory controller of claim 11, wherein the memory module is an ECC Dual In-line Memory Module (ECC-DIMM).

15. The memory controller of claim 11, wherein the memory controller further comprises:

an encoder unit coupled to the buffer and the control unit,

wherein the buffer is further operative by the control unit to;

receive a data content to be stored in the memory module through a plurality of successive memory accesses,

wherein the control unit is further operative to;

divide the data content into a plurality of access-specific data, wherein each access-specific data contains the first pre-determined number of bits, and

for each access-specific data, select an identical number of bits from each of the other access-specific data to generate an additional 56 bits of data, wherein a total of the first pre-determined number of bits and the additional 56 bits is at least 120,

wherein, for each memory access, the encoder unit is operative by the control unit to;

apply the SECDED (128,120) code to a combination of the access-specific data and the associated additional 56 bits of data to determine access-specific 8 bits of ECC,

wherein, during each successive memory access, the control unit is further operative to;

store the access-specific data along with the access-specific 8 bits of ECC in the memory module.

16. The memory controller of claim 15, wherein the plurality of bursts is eight bursts, and wherein the plurality of successive memory accesses is eight accesses.

17-19. -19. (canceled)

20. A system comprising:

a memory module configured to store electronic content; and

a processor coupled to the memory module and configured to perform a memory read operation on the memory module,

wherein, as part of the memory read operation, the processor is operative to perform the following;

receive a burst-specific content from each burst in a plurality of bursts from the memory module, wherein all bursts in the plurality of bursts together comprise the memory read operation, and wherein the burst-specific content includes a first pre-determined number of bits of burst-specific data along with corresponding bits of burst-specific Error Correcting Code (ECC),

store the burst-specific content from each burst in the plurality of bursts,

use all received ECC bits as part of a Single Error Correction Double Error Detection (SECDED) code to correct more than one error in the first pre-determined number of bits of burst-specific data from at least one of the plurality of bursts,

wherein, as part of using all the received ECC bits, the processor is further operative to perform the following for each burst in the plurality of bursts;

select a burst-specific second pre-determined number of bits of data from all other bursts in the plurality of bursts, wherein a total of the first pre-determined number of bits and the second pre-determined number of bits is at least 120, and

apply the bits of burst-specific ECC to the corresponding first pre-determined number of bits of burst-specific data as well as to the burst-specific second pre-determined number of bits of data.

21. The system of claim 20, wherein the processor is further configured to perform a memory write operation on the memory module, and

wherein, as part of the memory write operation, the processor is operative to perform the following:

prepare a data content to be stored in the memory module through a plurality of successive memory accesses, wherein all memory accesses in the plurality of successive accesses together comprise the memory write operation,

divide the data content into a plurality of access-specific data, wherein each access-specific data contains the first pre-determined number of bits,

for each access-specific data, select an additional second pre-determined number of bits of data from all other access-specific data in the plurality of access-specific data, wherein a total of the first pre-determined number of bits and the second pre-determined number of bits is at least 120,

for each memory access, apply the SECDED code to a combination of the access-specific data and associated additional second pre-determined number of bits of data to determine access-specific bits of ECC, and

during each successive memory access, store the access-specific data along with the access-specific bits of ECC in the memory module.

22. The system of claim 20, wherein the SECDED code is a SECDED (128,120) code.