SYSTEM AND METHOD FOR ADAPTIVELY ALLOCATING RESOURCES IN A TRANSCODER

• US 20160134880A1
• Filed: 01/19/2016
• Published: 05/12/2016
• Est. Priority Date: 09/22/2009
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Chengalvala, Vivekanand, Senicic, Djordje
• Granted Patent: US 10,511,848 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H04N 19/40 using video transcoding, i.e. partial or full decoding of a coded input stream followed by re-encoding of the decoded output stream
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/44 Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
• CPC Class Codes: H04N 19/70 characterised by syntax aspects related to video coding, e.g. related to compression standards

Abstract

An adaptive transcoder is provided that includes a shared memory containing a plurality of decoder buffers to store incoming data packets, a plurality of decoder instances to control a decoding process to generate image raw data based on the incoming data packets, and a plurality of encoder instances configured to control an encoding process to generate outgoing packets based on the image raw data; and a data processing element containing a plurality of processing cores, and a core controller. Each decoder instance is paired with an encoder instance; and each decoder buffer is associated with a decoder instance. Each decoder buffer includes a monitoring element to monitor a respective decoder buffer, and provide buffer data corresponding to the status of the decoder buffer. Each encoder instance is associated with a processing core; and the core controller uses the buffer data to associate each decoder instance with a processing core.

Claims

1-21. -21. (canceled)

22. An adaptive transcoder, comprising:

a shared memory containing a channel instance configured to provide instructions and memory for translating a plurality of incoming data packets from a first format to a second format; and

a data processing element configured to provide the data processing for translating the plurality of incoming data packets from the first format to the second format,

wherein the channel instance includes;

a decoder FIFO buffer configured to store the plurality of incoming data packets, and to provide FIFO data indicating how many packets are contained in the FIFO buffer and a warning indicator indicating whether the FIFO buffer has reached a first threshold of stored packets,

a decoder instance configured to control a decoding process from the first format to generate a plurality of image raw data based on the plurality of incoming data packets, and

an encoder instance configured to control an encoding process to generate a plurality of outgoing packets in the second format based on the image raw data,

wherein the data processing element includes

a plurality of processing cores, each configured to perform the decoding process based on the decoder instance, or the encoding process based on the encoder instance, and

a core controller is configured to assign of the decoder instance one of the plurality of processing cores.

23. The adaptive transcoder of claim 22, wherein the core controller is configured to assign the FIFO buffer and the decoder instance to the one of the plurality of processing cores of based on a value of the warning indicator.

24. The adaptive transcoder of claim 22, wherein the core controller is configured to control the encoding process to drop packets during encoding when the critical alert indicator indicates that the respective decoder buffer has reached the third threshold of stored packets.

25. The adaptive transcoder of claim 22,

wherein the channel instance further comprises an image processor instance configured to perform image processing operations on the image raw data after the decoding process and before the encoding processor, and

wherein the image processor instance is configured to reduce the amount of image processing performed during the image processing operations when the alert indicator indicates that the respective decoder buffer has reached the second threshold of stored packets.

26. The adaptive transcoder of claim 22, wherein the shared memory further comprises a plurality of channel instances.

27. An adaptive transcoder, comprising:

a shared memory containing a channel instance configured to provide instructions and memory for translating a plurality of incoming data packets from a first format to a second format; and

a data processing element configured to provide the data processing for translating the plurality of incoming data packets from the first format to the second format,

wherein the channel instance includes;

a decoder FIFO buffer configured to store the plurality of incoming data packets, and to provide FIFO data indicating how many packets are contained in the FIFO buffer and an alert indicator indicating whether the FIFO buffer has reached a second threshold of stored packets, the second threshold being greater than the first threshold,

a decoder instance configured to control a decoding process from the first format to generate a plurality of image raw data based on the plurality of incoming data packets, and

an encoder instance configured to control an encoding process to generate a plurality of outgoing packets in the second format based on the image raw data,

wherein the data processing element includes

a plurality of processing cores, each configured to perform the decoding process based on the decoder instance, or the encoding process based on the encoder instance, and

a core controller is configured to assign of the decoder instance one of the plurality of processing cores.

28. The adaptive transcoder of claim 27, wherein the core controller is configured to assign the FIFO buffer and the decoder instance to the one of the plurality of processing cores of based on a value of the warning indicator.

29. The adaptive transcoder of claim 27, wherein the core controller is configured to control the encoding process to drop packets during encoding when the critical alert indicator indicates that the respective decoder buffer has reached the third threshold of stored packets.

30. The adaptive transcoder of claim 27,

wherein the channel instance further comprises an image processor instance configured to perform image processing operations on the image raw data after the decoding process and before the encoding processor, and

wherein the image processor instance is configured to reduce the amount of image processing performed during the image processing operations when the alert indicator indicates that the respective decoder buffer has reached the second threshold of stored packets.

31. The adaptive transcoder of claim 27, wherein the shared memory further comprises a plurality of channel instances.

32. An adaptive transcoder, comprising:

a shared memory containing a channel instance configured to provide instructions and memory for translating a plurality of incoming data packets from a first format to a second format; and

a data processing element configured to provide the data processing for translating the plurality of incoming data packets from the first format to the second format,

wherein the channel instance includes;

a decoder FIFO buffer configured to store the plurality of incoming data packets, and to provide FIFO data indicating how many packets are contained in the FIFO buffer and a critical alert indicator indicating whether the FIFO buffer has reached a third threshold of stored packets, the third threshold being greater than the second threshold,

a decoder instance configured to control a decoding process from the first format to generate a plurality of image raw data based on the plurality of incoming data packets, and

an encoder instance configured to control an encoding process to generate a plurality of outgoing packets in the second format based on the image raw data,

wherein the data processing element includes

a plurality of processing cores, each configured to perform the decoding process based on the decoder instance, or the encoding process based on the encoder instance, and

a core controller is configured to assign of the decoder instance one of the plurality of processing cores.

33. The adaptive transcoder of claim 32, wherein the core controller is configured to assign the FIFO buffer and the decoder instance to the one of the plurality of processing cores of based on a value of the warning indicator.

34. The adaptive transcoder of claim 32, wherein the core controller is configured to control the encoding process to drop packets during encoding when the critical alert indicator indicates that the respective decoder buffer has reached the third threshold of stored packets.

35. The adaptive transcoder of claim 32,

wherein the channel instance further comprises an image processor instance configured to perform image processing operations on the image raw data after the decoding process and before the encoding processor, and

wherein the image processor instance is configured to reduce the amount of image processing performed during the image processing operations when the alert indicator indicates that the respective decoder buffer has reached the second threshold of stored packets.

36. The adaptive transcoder of claim 32, wherein the shared memory further comprises a plurality of channel instances.