IDENTIFYING INSTRUCTIONS FOR DECODE-TIME INSTRUCTION OPTIMIZATION GROUPING IN VIEW OF CACHE BOUNDARIES

• US 20160139927A1
• Filed: 06/09/2015
• Published: 05/19/2016
• Est. Priority Date: 11/17/2014
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: GSCHWIND, MICHAEL K., SALAPURA, VALENTINA
• Granted Patent: US 10,061,705 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 12/0886 Variable-length word access
• CPC Class Codes: G06F 2212/452 Instruction code
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/382 Pipelined decoding, e.g. using predecoding
• CPC Class Codes: G06F 9/3853 of compound instructions

Abstract

A technique for processing instructions includes examining instructions in an instruction stream of a processor to determine properties of the instructions. The properties indicate whether the instructions may belong in an instruction sequence subject to decode-time instruction optimization (DTIO). Whether the properties of multiple ones of the instructions are compatible for inclusion within an instruction sequence of a same group is determined. The instructions with compatible ones of the properties are grouped into a first instruction group. The instructions of the first instruction group are decoded subsequent to formation of the first instruction group. Whether the first instruction group actually includes a DTIO sequence is verified based on the decoding. Based on the verifying, DTIO is performed on the instructions of the first instruction group or is not performed on the instructions of the first instruction group.

Claims

1. A method of processing instructions in a processor core, the method comprising:

examining, by predecode logic, instructions in an instruction stream of a processor to determine properties of the instructions, wherein the properties indicate whether the instructions may belong in an instruction sequence subject to decode-time instruction optimization (DTIO);

determining, by grouping logic, whether the properties of multiple ones of the instructions are compatible for inclusion within an instruction sequence of a same group;

grouping, by the grouping logic, the instructions with compatible ones of the properties into a first instruction group;

decoding, by a decode unit, the instructions of the first instruction group subsequent to formation of the first instruction group;

verifying, by the decode unit, whether the first instruction group actually includes a DTIO sequence based on the decoding;

in response to the first instruction group actually including a DTIO sequence based on the verifying, performing, by the decode unit, DTIO on the instructions of the first instruction group; and

in response to the first instruction group not actually including a DTIO sequence based on the verifying, refraining from performing, by the decode unit, DTIO on the instructions of the first instruction group.

2. The method of claim 1, further comprising:

in response to an instruction in the instruction stream not being a boundary instruction, indicating, using the predecode logic, whether adjacent ones of the instructions should be grouped in a same instruction group based on the properties, wherein the boundary instruction is a last instruction before a cache boundary or a first instruction after a cache boundary;

in response to an instruction in the instruction stream being a boundary instruction, determining, using the predecode logic, a last property of the last instruction or a first property of the first instruction; and

indicating, using the predecode logic, the last property of the last instruction and the first property of the first instruction to facilitate instruction grouping.

3. The method of claim 2, further comprising:

grouping, using the grouping logic, the last instruction and the first instruction in the same instruction group in response to the first and last properties being compatible.

4. The method of claim 1, wherein the properties are indicated by fewer instruction bits than is required for a full instruction compare.

5. The method of claim 1, wherein the properties are associated with instruction classes and each instruction class property indicates whether a given one of the instructions is associated with one of a plurality of instruction sequences constituting an instruction class.

6. The method of claim 1, further comprising determining whether the instruction sequence to be contained within a single instruction group can be entirely contained within a present instruction group;

in response to determining the instruction sequence can be contained within the present instruction group, adding the instructions of the instruction sequence to the present instruction group;

in response to determining the instruction sequence cannot be contained within the present instruction group, ending the present instruction group and starting a new instruction group; and

adding the instructions of the instruction sequence to the new instruction group.

7. The method of claim 1, wherein the properties are associated with instruction registers.

8. The method of claim 1, wherein the properties are associated with instruction registers and instruction classes.

9. The method of claim 2, wherein the cache boundary is a cache sector boundary or a cache line boundary.

10. The method of claim 2, further comprising:

grouping, using the grouping logic, the last instruction and the first instruction in the same instruction group in response to the first and last properties being compatible and a feedback value generated by a feedback function indicating the same instruction group has been historically beneficial in improving performance of the processor.