CHIP PACKAGE AND METHOD FOR FORMING THE SAME

• US 20160141219A1
• Filed: 01/27/2016
• Published: 05/19/2016
• Est. Priority Date: 04/02/2014
• Status: Active Grant

• Current Assignee: Xintec Incorporated
• Original Assignee: Xintec Incorporated
• Inventors: LIU, Chien-Hung
• Granted Patent: US 9,704,772 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G01L 19/0061 Electrical connection means
• CPC Class Codes: G01L 19/06 Means for preventing overload or deleterious influence of the measured medium on the measuring device or vice versa
• CPC Class Codes: G01L 19/14 Housings G01L19/0007, G01L19/0084, G01L19/0092, G01L19/04, G01L19/06 take precedence
• CPC Class Codes: G06F 18/00 Pattern recognition
• CPC Class Codes: G06F 21/32 using biometric data, e.g. fingerprints, iris scans or voiceprints
• CPC Class Codes: G06V 40/12 Fingerprints or palmprints
• CPC Class Codes: H01L 2021/60022 using bump connectors, e.g. for flip chip mounting
• CPC Class Codes: H01L 21/0212 the material being fluoro carbon compounds, e.g.(CFx) n, (CHxFy) n or polytetrafluoroethylene
• CPC Class Codes: H01L 21/02263 deposition from the gas or vapour phase
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13116 Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 23/291 Oxides or nitrides or carbides, e.g. ceramics, glass
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3185 : the coating covering also the sidewalls of the semiconductor body
• CPC Class Codes: H01L 23/3192 : Multilayer coating
• CPC Class Codes: H01L 23/525 : with adaptable interconnections
• CPC Class Codes: H01L 24/00 : Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H05K 1/0298 : Multilayer circuits
• CPC Class Codes: H05K 1/111 : Pads for surface mounting, e.g. lay-out
• CPC Class Codes: H05K 1/181 : associated with surface mounted components
• CPC Class Codes: H05K 3/32 : electrically connecting electric components or wires to printed circuits

Abstract

A chip package includes a chip, a dam layer, a permanent adhesive layer, a support, a buffer layer, a redistribution layer, a passivation layer, and a conducting structure. A conducting pad and a sensing device of the chip are located on a first surface of a substrate of the chip, and the conducting pad protrudes from the side surface of the substrate. The dam layer surrounds the sensing device. The permanent adhesive layer is between the support and the substrate. The support and the permanent adhesive layer have a trench to expose the conducting pad. The buffer layer is located on the support. The redistribution layer is located on the buffer layer and on the support, the permanent adhesive layer, and the conducting pad facing the trench. The passivation layer covers the redistribution layer, the buffer layer, and the conducting pad.

Claims

1. A chip package, comprising:

a chip having a substrate, a conducting pad, and a sensing device, wherein the substrate has a side surface, a first surface, and a second surface opposite to the first surface, and the side surface is connected to the first and second surfaces, and the conducting pad and the sensing device are located on the first surface, and the conducting pad protrudes from the side surface;

a dam layer located on the first surface and surrounding the sensing device;

a permanent adhesive layer covering the second surface, the side surface, and the conducting pad that protrudes the side surface;

a support, wherein the permanent adhesive layer is between the support and the substrate, and the support and the permanent adhesive layer have a trench, such that the conducting pad protruding the side surface is exposed through the trench;

a buffer layer located on the support;

a redistribution layer located on the buffer layer and on the support, the permanent adhesive layer, and the conducting pad that face the trench;

a passivation layer covering the redistribution layer, the buffer layer, and the conducting pad that is exposed through the trench, wherein the passivation layer has an opening to expose the redistribution layer; and

a conducting structure located on the redistribution layer that is in the opening of the passivation layer.

2. The chip package of claim 1, further comprising:

a printed circuit board electrically connected to the conducting structure.

3. The chip package of claim 2, further comprising:

an isolation element located on the printed circuit board and surrounding the passivation layer and the dam layer.

4. The chip package of claim 3, further comprising:

a first dielectric layer located on the isolation element and the chip.

5. The chip package of claim 4, wherein the first dielectric layer is made of a material comprising titanium oxide or strontium titanate.

6. The chip package of claim 4, further comprising:

a second dielectric layer located on the first dielectric layer.

7. The chip package of claim 6, wherein hardness of the second dielectric layer is greater than hardness of the first dielectric layer.

8. The chip package of claim 2, further comprising:

a carrier located on the dam layer and covering the sensing device.

9. The chip package of claim 8, further comprising:

a temporary adhesive layer between the carrier and the dam layer.

10. The chip package of claim 1, wherein the support is made of a material comprising glass.

11. A manufacturing method of a chip package, comprising:

forming a dam layer on a conducting pad of a wafer, wherein the dam layer surrounds a sensing device of the wafer;

utilizing a temporary adhesive layer for bonding a carrier to the dam layer;

etching a substrate of the wafer, such that the conducting pad protrudes from a side surface of the substrate;

utilizing a permanent adhesive layer for bonding a support to the wafer, such that the permanent adhesive layer is between the support and the substrate;

forming a buffer layer on the support;

forming a trench in the buffer layer, the support, and the permanent adhesive layer, thereby exposing the conducting pad that protrudes from the side surface of the substrate;

forming a redistribution layer on the buffer layer and on the support, the permanent adhesive layer, and the conducting pad that face the trench;

forming a passivation layer for covering the redistribution layer, the buffer layer, and the conducting pad that is exposed through the trench, wherein the passivation layer has an opening; and

forming a conducting structure on the redistribution layer that is in the opening of the passivation layer.

12. The manufacturing method of the chip package of claim 11, further comprising:

cutting the carrier and the dam layer along the trench.

13. The manufacturing method of the chip package of claim 12, further comprising:

electrically connecting a printed circuit board to the conducting structure.

14. The manufacturing method of the chip package of claim 13, further comprising:

eliminating adhesion of the temporary adhesive layer; and

removing the carrier from the dam layer.

15. The manufacturing method of the chip package of claim 14, wherein eliminating the adhesion of the temporary adhesive layer comprises:

utilizing ultraviolet light for irradiating the temporary adhesive layer or immersing the temporary adhesive layer in a chemical liquid.

16. The manufacturing method of the chip package of claim 14, further comprising:

forming an isolation element on the printed circuit board, wherein the isolation element surrounds the passivation layer and the dam layer.

17. The manufacturing method of the chip package of claim 16, wherein the isolation element is formed by molding.

18. The manufacturing method of the chip package of claim 16, further comprising:

forming a first dielectric layer on the isolation element and the chip.

19. The manufacturing method of the chip package of claim 18, wherein the first dielectric layer is formed by coating, deposition, or printing.

20. The manufacturing method of the chip package of claim 18, further comprising:

forming a second dielectric layer on the first dielectric layer, wherein hardness of the second dielectric layer is greater than hardness of the first dielectric layer.