SEMICONDUCTOR DEVICE AND METHOD OF MAKING

• US 20160141394A1
• Filed: 01/26/2016
• Published: 05/19/2016
• Est. Priority Date: 11/27/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lu, Wen-Tai, Nieh, Chun-Feng, Chen, Hou-Yu, Lin, Yu-Chang
• Granted Patent: US 9,653,581 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66871 Processes wherein the final gate is made after the formation of the source and drain regions in the active layer, e.g. dummy-gate processes
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7847 using a memorization technique, e.g. re-crystallization under strain, bonding on a substrate having a thermal expansion coefficient different from the one of the region
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 2924/13067 FinFET, source/drain region shapes fins on the silicon surface

Abstract

A semiconductor device is provided. The semiconductor device includes a channel region disposed between a source region and a drain region, a gate structure over the channel region, an interlayer dielectric (ILD) layer proximate the gate structure, an ILD stress layer proximate the top portion of gate structure and over the ILD layer. The gate structure includes a first sidewall, a second sidewall and a top portion. A first stress memorization region is also provided. The first stress memorization region is proximate the top portion of the gate structure. A method of making a semiconductor device is also provided.

Claims

1. A method of forming a semiconductor device, comprising:

etching a substrate to define a fin structure;

forming a dummy gate structure over a channel region of the fin structure;

forming an interlayer dielectric (ILD) layer over a source/drain region in contact with the channel region;

implanting a dopant into a portion of the ILD layer to define an implanted ILD layer over a second portion of the ILD layer in which the dopant is not implanted; and

annealing the implanted ILD layer to stress the implanted ILD layer, wherein the stress applies a compressive force on the dummy gate structure.

2. The method of claim 1, wherein the etching comprises etching the substrate to define a second fin structure, and the method comprises:

forming an isolation structure over the substrate and between the fin structure and the second fin structure.

3. The method of claim 1, comprising:

etching a portion of the fin structure not covered by the dummy gate structure to define a fin recess.

4. The method of claim 3, comprising:

growing an epi-region in the fin recess, the epi-region corresponding to the source/drain region.

5. The method of claim 1, comprising:

depositing a contact etch stop layer (CESL) over the source/drain region prior to the forming an ILD layer.

6. The method of claim 1, comprising:

depositing a contact etch stop layer (CESL) over the source/drain region and the dummy gate structure prior to the forming an ILD layer.

7. The method of claim 6, wherein the forming an ILD layer comprises:

forming the ILD layer over the CESL, the ILD layer overlying the source/drain region and the dummy gate structure.

8. The method of claim 1, wherein the forming a dummy gate structure comprises:

depositing a dummy poly layer.

9. The method of claim 8, wherein the implanting comprises:

implanting the dopant into a portion of the dummy poly layer to define an implanted dummy poly layer over a second portion of the dummy poly layer in which the dopant is not implanted.

10. The method of claim 9, wherein annealing comprises:

annealing the implanted dummy poly layer.

11. The method of claim 10, wherein annealing the implanted dummy poly layer causes an amorphous part of the implanted dummy poly layer to be recrystallized.

12. The method of claim 10, wherein recrystallization of the implanted dummy poly layer causes a compressive force to be applied to the channel region.

13. The method of claim 1, wherein the compressive force on the dummy gate structure causes a second compressive force to be applied to the channel region.

14. The method of claim 1, comprising:

replacing the dummy gate structure with a gate structure after the annealing.

15. A method of forming a semiconductor device, comprising:

etching a substrate to define a fin structure;

forming a dummy gate structure over a channel region of the fin structure, the dummy gate structure comprising a dummy poly layer;

implanting a dopant into a portion of the dummy poly layer to define an implanted dummy poly layer over a second portion of the dummy poly layer in which the dopant is not implanted; and

annealing the implanted dummy poly layer to recrystallize the implanted dummy poly layer, wherein recrystallization of the implanted dummy poly layer causes a compressive force to be applied to the channel region.

16. The method of claim 15, comprising:

etching a portion of the fin structure not covered by the dummy gate structure to define a fin recess; and

growing an epi-region in the fin recess, the epi-region corresponding to a source/drain region.

17. The method of claim 16, comprising:

forming an interlayer dielectric (ILD) layer over a source/drain region; and

implanting the dopant into a portion of the ILD layer to define an implanted ILD layer over a second portion of the ILD layer in which the dopant is not implanted.

18. The method of claim 17, wherein the annealing comprises:

annealing the implanted ILD layer to stress the implanted ILD layer, wherein the stress applies a compressive force on the dummy gate structure.

19. The method of claim 18, wherein the compressive force on the dummy gate structure causes a second compressive force to be applied to the channel region.

20. A method of forming a semiconductor device, comprising:

etching a substrate to define a fin structure;

forming a dummy gate structure over a channel region of the fin structure, the dummy gate structure comprising a dummy poly layer;

growing an epi-region adjacent the channel region, the epi-region corresponding to a source/drain region;

forming an interlayer dielectric (ILD) layer over the source/drain region;

implanting a dopant into a portion of the ILD layer to define an implanted ILD layer over a second portion of the ILD layer in which the dopant is not implanted and into a portion of the dummy poly layer to define an implanted dummy poly layer over a second portion of the dummy poly layer in which the dopant is not implanted; and

annealing the implanted ILD layer and the implanted dummy poly layer to stress the implanted ILD layer and to recrystallize the implanted dummy poly layer.