SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

• US 20160141407A1
• Filed: 11/10/2015
• Published: 05/19/2016
• Est. Priority Date: 11/14/2014
• Status: Active Grant

• Current Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Original Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Inventors: CHIBA, Akira
• Granted Patent: US 9,653,304 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/30 characterised by the memory core region

Abstract

A method of manufacturing a semiconductor device is provided, the method including forming a first gate member on a semiconductor substrate through a gate insulating film, forming a spacer on the first gate member, flattening a surface of the spacer, forming a first gate by partially etching the first gate member using the spacer as a mask, forming a second gate member so as to cover the first gate and the spacer having the flattened surface, forming a first insulating film on a surface of the second gate member, and forming a second gate by causing the second gate member to retreat while removing the first insulating film by etching.

Claims

1. A method of manufacturing a semiconductor device comprising:

forming a first gate member on a semiconductor substrate through a gate insulating film;

forming a spacer on the first gate member;

flattening a surface of the spacer;

forming a first gate by partially etching the first gate member using the spacer as a mask;

forming a second gate member so as to cover the first gate and the spacer having the flattened surface;

forming a first insulating film on a surface of the second gate member; and

forming a second gate by causing the second gate member to retreat while removing the first insulating film by etching.

2. The manufacturing method according to claim 1, further comprising:

forming a second insulating film so as to cover the second gate;

forming a side wall, which abuts a side surface of the second gate, by causing the second insulating film to retreat by etching; and

forming a metal compound layer on an upper surface of the second gate after the side wall is formed.

3. The manufacturing method according to claim 1,

wherein flattening the surface of the spacer is performed by chemical mechanical polishing.

4. The manufacturing method according to claim 1,

wherein, in flattening the surface of the spacer, the surface of the spacer is processed so as to be substantially parallel to the principal plane of the semiconductor substrate.

5. The manufacturing method according to claim 1, further comprising:

forming a mask which includes an opening on the first gate member,

wherein forming the spacer includes forming a spacer member so as to fill the opening, and causing the spacer member to retreat by etching.

6. The manufacturing method according to claim 1, further comprising:

forming a source and a drain at positions between which the first gate and the second gate of the semiconductor substrate are interposed.

7. The manufacturing method according to of claim 6,

wherein the first insulating film constitutes a gate insulating film of a semiconductor element other than a semiconductor element including the first gate, the second gate, the source, and the drain.

8. The manufacturing method according to claim 2, further comprising:

forming a source and a drain at positions between which the first gate and the second gate of the semiconductor substrate are interposed; and

forming a source wiring which is electrically connected to the source,

wherein, in forming the metal compound layer on the upper surface of the second gate, the metal compound layer is formed on an upper surface of the source wiring and an upper surface of the drain.

9. The manufacturing method according to claim 5,

wherein the spacer includes a pair of spacer pieces which are disposed to be separated in the opening, and

the method further comprises:

forming a source and a drain at positions between which the first gate and the second gate of the semiconductor substrate are interposed;

forming a wiring material which is electrically connected to the source so as to fill a gap between the pair of spacer pieces; and

forming a source wiring by etching the wiring material such that the height of the upper surface is lower than the height of the spacer before the surface of the spacer is flattened.

10. A semiconductor device comprising:

a semiconductor substrate;

a first gate that is provided on the semiconductor substrate through a gate insulating film;

a spacer that is provided on the first gate and has a flattened surface;

a second gate that is provided on the semiconductor substrate and adjacent to the first gate and the spacer;

a source and a drain that are provided at positions between which the first gate and the second gate are interposed;

a source wiring that is electrically connected to the source; and

a metal compound layer that is provided on each of an upper surface of the second gate, an upper surface of the source wiring, and an upper surface of the drain.

11. The semiconductor device according to claim 10,

wherein the flattened surface of the first gate is substantially parallel to the principal plane of the semiconductor substrate.