CALIBRATING OPTIMAL READ LEVELS

• US 20160148702A1
• Filed: 11/20/2014
• Published: 05/26/2016
• Est. Priority Date: 11/20/2014
• Status: Active Grant

• Current Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Original Assignee: HGST Netherlands B.V. (Western Digital Corporation)
• Inventors: KARAKULAK, Seyhan, WEATHERS, Anthony Dwayne, BARNDT, Richard David
• Granted Patent: US 9,576,671 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters

Abstract

After a predetermined period of time in a life cycle of a flash memory device, a plurality of reliability values corresponding to a plurality of reads of one or more of the plurality of memory cells are generated; each of the reads using a variation of a predetermined read level voltage. An offset voltage is then identified, offset from the read level voltage. The offset voltage corresponds to a zero crossing point in the range of the reliability values. Once the offset voltage is identified, the read level voltage is set to a calibrated voltage based on the offset voltage.

Claims

1. A machine-implemented method, comprising:

after a predetermined period of time in a life cycle of a flash memory device, reading a plurality of memory cells of the flash memory device a plurality of times, each of the reads using a read level voltage adjusted by a respective one of a plurality of read level offset voltages;

identifying an offset voltage, offset from the read level voltage, that corresponds to a zero crossing point in a range of reliability values corresponding to the plurality of read memory cells; and

setting the read level voltage to a calibrated voltage based on the offset voltage.

2. The machine-implemented method of claim 1, further comprising:

storing the plurality of predetermined read level offsets, each predetermined read level offset being associated with a group of wordlines in the flash memory device for use with the read level voltage in reading memory cells in the group of wordlines;

for a respective group of wordlines, updating a read level offset previously stored for the group with the identified offset voltage; and

in connection with a read operation, retrieving the updated read level offset to set the read level voltage to the calibrated voltage, and using the read level voltage set to the calibrated voltage to read the respective group of wordlines.

3. The machine-implemented method of claim 1, further comprising:

identifying a wordline associated with the plurality of memory cells that is associated with an error rate that exceeds an error threshold;

in response to identifying the wordline, reading memory cells in one or more wordlines adjacent to the identified wordline to generate the plurality of reliability values, identify the offset voltage, and set the read level voltage; and

re-read the identified wordline using the read level voltage set to the calibrated voltage.

4. The machine-implemented method of claim 1, further comprising:

identifying a first codeword associated with the plurality of memory cells, the first codeword being associated with an error rate that exceeds an error threshold;

in response to identifying the first codeword, reading memory cells in one or more second codewords adjacent to the first codeword to generate the plurality of reliability values, identify the offset voltage, and set the read level voltage; and

re-read the first codeword using the read level voltage set to the calibrated voltage.

5. The machine-implemented method of claim 1, wherein setting the read level voltage to the calibrated voltage comprises:

adjusting the read level voltage by the identified offset voltage to read memory cells across a plurality of memory channels, wherein each channel is configured to address one or more memory blocks.

6. The machine-implemented method of claim 5, wherein setting the read level voltage to the calibrated voltage further comprises:

associating the identified offset voltage with all blocks and all pages in the flash memory device that are addressable by the plurality of memory channels so that the read level is adjusted by the identified offset voltage when reading memory cells of any page or block associated with the plurality of memory channels.

7. The machine-implemented method of claim 5, wherein setting the read level voltage to the calibrated voltage further comprises:

associating the identified offset voltage with a page address; and

adjusting the read level by the identified offset voltage when reading memory cells associated with the page address via any of the plurality of memory channels, each page address addressable via the plurality of memory channels being associated with a different offset voltage.

8. The machine-implemented method of claim 1, wherein for the plurality of reliability values, a positive reliability value is indicative of a corresponding output state being a binary 0, and a negative reliability value is indicative of the corresponding output state being a binary 1.

9. The machine-implemented method of claim 1, wherein each generated reliability value is indicative of a likelihood that an output state of the memory cells is equal to one of multiple predetermined programmed states.

10. The machine-implemented method of claim 1, further comprising:

determining the zero crossing point based on an interpolation of the reliability values.

11. A data storage system, comprising:

a plurality of flash memory devices, each flash memory device comprising a plurality of memory blocks; and

a controller coupled to the plurality of flash memory devices, wherein the controller is configured to;

provide a read level voltage to read memory cells that are programmed to a programming level;

after a predetermined number of program/erase cycles, read the memory cells a plurality of times, each of the reads using a read level voltage adjusted by a respective one or a plurality of read level offset voltages;

identify an offset voltage, offset from the read level voltage, that corresponds to a zero crossing point in a range of reliability values corresponding to the plurality of read memory cells; and

set the read level voltage to a calibrated voltage based on the offset voltage.

12. The data storage system of claim 11, wherein the controller is further configured to:

store the plurality of predetermined read level offsets, each predetermined read level offset being associated with a group of wordlines for use with the read level voltage in reading memory cells in the group of wordlines;

for a respective group of wordlines, update a read level offset previously stored for the group with the identified offset voltage; and

in connection with a read operation, retrieve the updated read level offset to set the read level voltage to the calibrated voltage, and using the read level voltage set to the calibrated voltage to read the respective group of wordlines.

13. The data storage system of claim 11, wherein the controller is further configured to:

identify a wordline associated with an error rate that satisfies an error threshold;

in response to identifying the wordline, reading memory cells in one or more wordlines adjacent to the identified wordline to generate the plurality of reliability values, identify the offset voltage and set the read level voltage, the one or more adjacent wordlines comprising the plurality of memory cells; and

re-read the identified wordline using the read level voltage set to the calibrated voltage.

14. The data storage system of claim 11, wherein the controller is further configured to:

identify a first codeword associated with an error rate that satisfies an error threshold;

in response to identifying the first codeword, reading memory cells in one or more second codewords adjacent to the first codeword to generate the plurality of reliability values, identify the offset voltage and set the read level voltage, the one or more second codewords comprising the plurality of memory cells; and

re-read the first codeword using the read level voltage set to the calibrated voltage.

15. The data storage system of claim 11, wherein setting the read level voltage to the calibrated voltage comprises:

adjusting the read level voltage by the identified offset voltage to read memory cells across a plurality of memory channels, wherein each channel is configured to address one or more memory blocks.

16. The data storage system of claim 15, wherein the controller is further configured to:

associate the identified offset voltage with all blocks and all pages addressable by the plurality of memory channels so that the read level is adjusted by the identified offset voltage when reading memory cells of any page or block associated with the plurality of memory channels.

17. The data storage system of claim 11, wherein the controller is further configured to:

associating the identified offset voltage with a page address; and

adjusting the read level by the identified offset voltage when reading memory cells associated with the page address via any of the plurality of memory channels, each page address addressable via the plurality of memory channels being associated with a different offset voltage.

18. A machine-implemented method, comprising:

providing a read level for reading memory cells of a flash memory device that are programmed to a programming level;

after a predetermined number of program/erase cycles, reading one or more of the memory cells a plurality of times to generate a plurality of reliability values, each of the reads using a read level adjusted by a respective one or a plurality of read level offsets;

identifying an offset from the read level that corresponds to a zero crossing point in the range of the reliability values; and

adjusting the read level based on the offset.

19. The machine-implemented method of claim 18, further comprising:

storing the plurality of predetermined read level offsets, each predetermined read level offset being associated with a group of wordlines in the flash memory device and for use with the read level in reading memory cells in the group of wordlines;

for a respective group of wordlines, updating a read level offset previously stored for the group with the identified offset; and

in connection with a read operation, retrieving the updated read level offset to adjust the read level, and using the adjusted read level to read the respective group of wordlines.

20. The machine-implemented method of claim 18, further comprising:

determining that reading a wordline or codeword associated with the memory cells has generated an error rate exceeding an error threshold;

in response to the determining, reading memory cells in one or more wordlines adjacent to the identified wordline or codeword to generate the plurality of reliability values, identify the offset, and set the read level; and

re-read the identified wordline or codeword using the adjusted read level.