DUAL EPITAXY CMOS PROCESSING USING SELECTIVE NITRIDE FORMATION FOR REDUCED GATE PITCH
First Claim
1. A method of forming a complementary metal oxide semiconductor (CMOS) device structure, the method comprising:
- forming a spacer layer material over a substrate and over gate structures defined in both a first polarity type region and a second polarity type region of the substrate;
selectively etching the spacer layer material in the first polarity type region to form first gate sidewall spacers, leaving the spacer layer material in the second polarity type region intact;
forming first epitaxially grown source/drain (SD) regions in the first polarity type region;
selectively forming a protection layer only on exposed surfaces of the first epitaxially grown SD regions, so as not to increase a thickness of the spacer layer material in the second polarity type region;
forming a masking layer over the first polarity type region, and etching the spacer layer material in the second polarity type region to form second gate sidewall spacers; and
removing the masking layer and forming second epitaxially grown SD regions in the second polarity type region, wherein the selectively formed protection layer prevents additional growth of epitaxial material on the first epitaxially grown SD regions.
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Abstract
A method of forming a complementary metal oxide semiconductor (CMOS) device structure includes forming a spacer layer material over a substrate and over gate structures defined in a first polarity type region and a second polarity type region; selectively etching the spacer layer material in the first polarity type region to form first gate sidewall spacers; forming first epitaxially grown source/drain (SD) regions in the first polarity type region; selectively forming a protection layer only on exposed surfaces of the first SD regions, so as not to increase a thickness of the spacer layer material in the second polarity type region; forming a masking layer over the first polarity type region, and etching the spacer layer material in the second polarity type region to form second gate sidewall spacers; and removing the masking layer and forming second epitaxially grown SD regions in the second polarity type region.
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Citations
22 Claims
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1. A method of forming a complementary metal oxide semiconductor (CMOS) device structure, the method comprising:
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forming a spacer layer material over a substrate and over gate structures defined in both a first polarity type region and a second polarity type region of the substrate; selectively etching the spacer layer material in the first polarity type region to form first gate sidewall spacers, leaving the spacer layer material in the second polarity type region intact; forming first epitaxially grown source/drain (SD) regions in the first polarity type region; selectively forming a protection layer only on exposed surfaces of the first epitaxially grown SD regions, so as not to increase a thickness of the spacer layer material in the second polarity type region; forming a masking layer over the first polarity type region, and etching the spacer layer material in the second polarity type region to form second gate sidewall spacers; and removing the masking layer and forming second epitaxially grown SD regions in the second polarity type region, wherein the selectively formed protection layer prevents additional growth of epitaxial material on the first epitaxially grown SD regions. - View Dependent Claims (2, 3, 4, 5, 21)
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6. A method of forming a complementary metal oxide semiconductor (CMOS) device structure, the method comprising:
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forming a nitride spacer layer material over a substrate and over gate structures defined in both a first polarity type region and a second polarity type region of the substrate; selectively etching the nitride spacer layer material in the first polarity type region to form first gate sidewall spacers, leaving the nitride spacer layer material in the second polarity type region intact; forming first epitaxially grown source/drain (SD) regions in the first polarity type region; selectively forming a nitride protection layer only on exposed surfaces of the first epitaxially grown SD regions using a gas cluster ion beam (GCIB) process, so as not to increase a thickness of the nitride spacer layer material in the second polarity type region; forming a masking layer over the first polarity type region, and etching the nitride spacer layer material in the second polarity type region to form second gate sidewall spacers; and removing the masking layer and forming second epitaxially grown SD regions in the second polarity type region, wherein the selectively formed protection layer prevents additional growth of epitaxial material on the first epitaxially grown SD regions. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13, 14, 15, 22)
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16-20. -20. (canceled)
Specification