DUAL EPITAXY CMOS PROCESSING USING SELECTIVE NITRIDE FORMATION FOR REDUCED GATE PITCH

• US 20160148933A1
• Filed: 11/24/2014
• Published: 05/26/2016
• Est. Priority Date: 11/24/2014
• Status: Active Grant

• Current Assignee: Elpis Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Khakifirooz, Ali, Wise, Richard S.
• Granted Patent: US 9,691,900 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02247 formation by nitridation, e.g. nitridation of the substrate
• CPC Class Codes: H01L 21/02252 formation by plasma treatment, e.g. plasma oxidation of the substrate after treatment of an insulating film by plasma H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/2236 from or into a plasma phase
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/26566 of a cluster, e.g. using a gas cluster ion beam
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A method of forming a complementary metal oxide semiconductor (CMOS) device structure includes forming a spacer layer material over a substrate and over gate structures defined in a first polarity type region and a second polarity type region; selectively etching the spacer layer material in the first polarity type region to form first gate sidewall spacers; forming first epitaxially grown source/drain (SD) regions in the first polarity type region; selectively forming a protection layer only on exposed surfaces of the first SD regions, so as not to increase a thickness of the spacer layer material in the second polarity type region; forming a masking layer over the first polarity type region, and etching the spacer layer material in the second polarity type region to form second gate sidewall spacers; and removing the masking layer and forming second epitaxially grown SD regions in the second polarity type region.

Claims

1. A method of forming a complementary metal oxide semiconductor (CMOS) device structure, the method comprising:

forming a spacer layer material over a substrate and over gate structures defined in both a first polarity type region and a second polarity type region of the substrate;

selectively etching the spacer layer material in the first polarity type region to form first gate sidewall spacers, leaving the spacer layer material in the second polarity type region intact;

forming first epitaxially grown source/drain (SD) regions in the first polarity type region;

selectively forming a protection layer only on exposed surfaces of the first epitaxially grown SD regions, so as not to increase a thickness of the spacer layer material in the second polarity type region;

forming a masking layer over the first polarity type region, and etching the spacer layer material in the second polarity type region to form second gate sidewall spacers; and

removing the masking layer and forming second epitaxially grown SD regions in the second polarity type region, wherein the selectively formed protection layer prevents additional growth of epitaxial material on the first epitaxially grown SD regions.

2. The method of claim 1, wherein selectively forming a protection layer only on exposed surfaces of the first epitaxially grown SD regions comprises a gas cluster ion beam (GCIB) process.

3. The method of claim 1, wherein the spacer layer material comprises a low-k material.

4. The method of claim 1, wherein adjacent gate structures have a pitch spacing ranging from about 35 nanometers (nm) to about 70 nm.

5. The method of claim 4, wherein the spacer layer material is formed at a thickness of about 9 nm such that an opening between adjacent gate structures is about 12 nm.

21. The method of claim 1, wherein the protection layer comprises one of an oxide or nitride material.

6. A method of forming a complementary metal oxide semiconductor (CMOS) device structure, the method comprising:

forming a nitride spacer layer material over a substrate and over gate structures defined in both a first polarity type region and a second polarity type region of the substrate;

selectively etching the nitride spacer layer material in the first polarity type region to form first gate sidewall spacers, leaving the nitride spacer layer material in the second polarity type region intact;

forming first epitaxially grown source/drain (SD) regions in the first polarity type region;

selectively forming a nitride protection layer only on exposed surfaces of the first epitaxially grown SD regions using a gas cluster ion beam (GCIB) process, so as not to increase a thickness of the nitride spacer layer material in the second polarity type region;

forming a masking layer over the first polarity type region, and etching the nitride spacer layer material in the second polarity type region to form second gate sidewall spacers; and

removing the masking layer and forming second epitaxially grown SD regions in the second polarity type region, wherein the selectively formed protection layer prevents additional growth of epitaxial material on the first epitaxially grown SD regions.

7. The method of claim 6, wherein adjacent gate structures have a pitch spacing of about 45 nanometers (nm).

8. The method of claim 7, wherein the nitride spacer layer material is formed at a thickness of about 9 nm such that an opening between adjacent gate structures is about 12 nm.

9. The method of claim 6, wherein the GCIB process is performed at room temperature.

10. The method of claim 6, wherein the first gate sidewall spacers and the second gate sidewall spacers have a same width.

11. The method of claim 6, wherein the nitride protection layer remains only on exposed surfaces of the first epitaxially grown SD regions during subsequent processing operations.

12. The method of claim 6, wherein the first polarity type region is an NFET region and the first epitaxially grown SD regions are formed from a material a selected to provide a tensile stress on an NFET channel.

13. The method of claim 12, wherein first epitaxially grown SD regions are silicon carbon (Si:

C).

14. The method of claim 6, wherein the second polarity type region is a PFET region and the second epitaxially grown SD regions are formed from a material a selected to provide a compressive stress on a PFET channel.

15. The method of claim 14, wherein second epitaxially grown SD regions are silicon germanium (SiGe).

22. The method of claim 6, wherein the protection layer is in direct contact with epitaxial material of the first epitaxially grown SD regions.

16-20. -20. (canceled)