SEMICONDUCTOR DEVICE INCLUDING A SUPERLATTICE AND REPLACEMENT METAL GATE STRUCTURE AND RELATED METHODS

• US 20160149023A1
• Filed: 11/23/2015
• Published: 05/26/2016
• Est. Priority Date: 11/25/2014
• Status: Active Grant

• Current Assignee: Atomera Incorporated
• Original Assignee: Mears Technologies Incorporated
• Inventors: Mears, Robert J., King Liu, Tsu-Jae, Takeuchi, Hideki
• Granted Patent: US 9,722,046 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 29/0642 Isolation within the component, i.e. internal isolation
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/152 with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
• CPC Class Codes: H01L 29/154 comprising at least one long range structurally disordered material, e.g. one-dimensional vertical amorphous superlattices
• CPC Class Codes: H01L 29/155 Comprising only semiconductor materials H01L29/154 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66431 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT with an active layer made of a group 13/15 material H01L29/66462
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/7782 with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET

Abstract

A semiconductor device may include a substrate having a channel recess therein, a plurality of spaced apart shallow trench isolation (STI) regions in the substrate, and source and drain regions spaced apart in the substrate and between a pair of the STI regions. A superlattice channel may be in the channel recess of the substrate and extend between the source and drain regions, with the superlattice channel including a plurality of stacked group of layers, and each group of layers of the superlattice channel including stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A replacement gate may be over the superlattice channel.

Claims

1. A method for making a semiconductor device comprising:

forming a plurality of spaced apart shallow trench isolation (STI) regions in a substrate;

forming a dummy gate on the substrate between a pair of the STI regions;

forming source and drain regions in the substrate on opposing sides of the dummy gate and between the pair of STI regions;

forming a dielectric layer on the substrate surrounding the dummy gate;

removing the dummy gate and portions of the substrate beneath the dummy gate to define a channel recess in the substrate between the source and drain regions;

forming a superlattice channel in the channel recess including a plurality of stacked groups of layers, each group of layers of the superlattice channel comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions; and

forming a replacement gate over the superlattice channel and removing the dielectric layer.

2. The method of claim 1 further comprising performing a well implant in the substrate between the pair of STI regions.

3. The method of claim 1 wherein forming the replacement gate comprises forming a high K dielectric layer over the superlattice channel, and forming a metal gate electrode over the high K dielectric layer.

4. The method of claim 1 wherein each base semiconductor portion comprises silicon.

5. The method of claim 1 wherein each base semiconductor portion comprises germanium.

6. The method of claim 1 wherein the at least one non-semiconductor layer comprises oxygen.

7. The method of claim 1 wherein the at least one non-semiconductor monolayer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.

8. The method of claim 1 wherein the superlattice channel further comprises a base semiconductor cap layer on an uppermost group of layers.

9. The method of claim 1 wherein at least some semiconductor atoms from opposing base semiconductor portions are chemically bound together through the at least one non-semiconductor monolayer therebetween.

10. A semiconductor device comprising:

a substrate having a channel recess therein;

a plurality of spaced apart shallow trench isolation (STI) regions in said substrate;

source and drain regions spaced apart in the substrate and between a pair of the STI regions; and

a superlattice channel in the channel recess of said substrate and extending between the source and drain regions, the superlattice channel including a plurality of stacked groups of layers, each group of layers of the superlattice channel comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions; and

a replacement gate over the superlattice channel.

11. The semiconductor device of claim 10 further comprising a well implant in the substrate between the pair of STI regions.

12. The semiconductor device of claim 10 wherein the replacement gate comprises:

a high K dielectric layer over the superlattice channel; and

a metal gate electrode over the high K dielectric layer.

13. The semiconductor device of claim 10 wherein each base semiconductor portion comprises silicon.

14. The semiconductor device of claim 10 wherein each base semiconductor portion comprises germanium.

15. The semiconductor device of claim 10 wherein the at least one non-semiconductor layer comprises oxygen.

16. The semiconductor device of claim 10 wherein the at least one non-semiconductor monolayer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.

17. The semiconductor device of claim 10 wherein the superlattice channel further comprises a base semiconductor cap layer on an uppermost group of layers.

18. The semiconductor device of claim 10 wherein at least some semiconductor atoms from opposing base semiconductor portions are chemically bound together through the at least one non-semiconductor monolayer therebetween.

19. A semiconductor device comprising:

a substrate having a channel recess therein;

a plurality of spaced apart shallow trench isolation (STI) regions in said substrate;

source and drain regions spaced apart in the substrate and between a pair of the STI regions;

a superlattice channel in the channel recess of said substrate and extending between the source and drain regions, the superlattice channel including a plurality of stacked groups of layers, each group of layers of the superlattice channel comprising a plurality of stacked silicon monolayers defining a base silicon portion and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions; and

a replacement gate comprising a high K dielectric layer over the superlattice channel and a metal gate electrode over the high K dielectric layer.

20. The semiconductor device of claim 19 further comprising a well implant in the substrate between the pair of STI regions.

21. The semiconductor device of claim 19 wherein the superlattice channel further comprises a base silicon cap layer on an uppermost group of layers.

22. The semiconductor device of claim 19 wherein at least some semiconductor atoms from opposing base silicon portions are chemically bound together through the at least one oxygen monolayer therebetween.